公开(公告)号：US20240264859A1

公开(公告)日：2024-08-08

申请号：US18422598

申请日：2024-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunwoo SIM ,  Hyunpil KIM ,  Seongwoo AHN

IPC: G06F9/48 ,  G06F9/30

CPC classification number: G06F9/4812 ,  G06F9/30105

Abstract: A processor includes a register file, a context controller that, in response to a target interrupt occurring, is configured to determine, a target register that stores new data acquired through each of commands for executing an interrupt service routine (ISR) among the plurality of registers, a write buffer configured to transmit pre-data stored in the target register to a memory, and a flag register configured to store set data including set values indicating whether the new data is stored in each of the registers. The context controller is configured to determine whether to transfer the pre-data to the memory through the write buffer based on the set data.

公开(公告)号：US20170068518A1

公开(公告)日：2017-03-09

申请号：US15134842

申请日：2016-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunpil KIM ,  Seongwoo AHN

IPC: G06F7/48 ,  G06F7/523

CPC classification number: G06F7/4812 ,  G06F7/523 ,  G06F7/5324 ,  G06F7/57

Abstract: Methods and apparatuses for performing arithmetic operations efficiently and quickly are described. Such arithmetic operations include, but are not limited to, multiplying 2N bit integers, multiplying multiple N-bit integers simultaneously, multiplying 2N bit complex numbers, and other multiplication operations involving coefficients, complex numbers, and complex conjugate numbers.

Abstract translation: 描述用于有效和快速地执行算术运算的方法和装置。 这种算术运算包括但不限于乘以2N位整数，同时乘以多个N位整数，乘以2N位复数，以及涉及系数，复数和复共轭数的其他乘法运算。

公开(公告)号：US20210312269A1

公开(公告)日：2021-10-07

申请号：US17223324

申请日：2021-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunpil KIM ,  Seongwoo AHN ,  Jonghyup LEE

IPC: G06N3/063 ,  G06N3/04 ,  G06F17/16 ,  G06F7/483 ,  G06N3/08

Abstract: A neural network device for performing a neural network operation includes a floating point arithmetic circuit configured to perform a dot-product operation for each of a plurality of floating point data pairs, wherein the floating point arithmetic circuit is configured to, in the dot-product operation, align-shift a plurality of fraction part multiplying operation results respectively corresponding to the floating point data pairs based on a maximum value determined from a plurality of exponent part adding operation results respectively corresponding to the floating point data pairs.

公开(公告)号：US20210273681A1

公开(公告)日：2021-09-02

申请号：US17322397

申请日：2021-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangwoon ROH ,  Sanguk PARK ,  Jinyoung PARK ,  Myunggyun YOON ,  Heonsoon JANG ,  Seyeong CHEON ,  Hyunpil KIM ,  Hwanjin KIM

IPC: H04B5/00 ,  H04B5/04 ,  H04W76/14 ,  H04W4/80

Abstract: An electronic device includes a communication interface operable to perform contactless communication with an external device; and a processor operable to control to determine a communication type to be performed with the external device; when the communication type is a first type of continuous communication, configure data in a long packet structure; when the communication type is a second type of discontinuous communication, configure data in a short packet structure; and perform data communication in the continuous communication or in the discontinuous communication with the external device on the basis of the determined communication type.