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    SEMICONDUCTOR DEVICE INCLUDING CHANNEL STRUCTURE AND THROUGH ELECTRODE, ELECTRONIC SYSTEM, AND METHOD OF FORMING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING CHANNEL STRUCTURE AND THROUGH ELECTRODE, ELECTRONIC SYSTEM, AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20230066367A1

    公开(公告)日：2023-03-02

    申请号：US17693328

    申请日：2022-03-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinyoung PARK ,  Hyuk KIM ,  Yeongeun YOOK

    IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528

    Abstract: A semiconductor device includes a lower structure including lower wirings. A horizontal wiring layer is disposed on the lower structure while including a horizontal conductive layer, and a horizontal insulating layer extending through the horizontal conductive layer. A stack structure is disposed on the horizontal wiring layer. A channel structure extending into the horizontal wiring layer while extending through the stack structure is provided. A through electrode connected to the lower wirings while extending through the stack structure and the horizontal insulating layer is provided. The stack structure includes insulating layers and electrode layers repeatedly alternately stacked, and an interlayer insulating layer disposed at side surfaces of the insulating layers and the electrode layers. The through electrode includes a first portion extending into the interlayer insulating layer, and a second portion disposed between the first portion and the lower wirings while having a smaller horizontal width than the first portion.

    METHOD FOR LAYOUT DESIGN AND SEMICONDUCTOR DEVICE MANUFACTURED BASED ON THE SAME
    3.
    发明申请
    METHOD FOR LAYOUT DESIGN AND SEMICONDUCTOR DEVICE MANUFACTURED BASED ON THE SAME 审中-公开

    公开(公告)号：US20200380197A1

    公开(公告)日：2020-12-03

    申请号：US16996044

    申请日：2020-08-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinyoung PARK

    IPC: G06F30/398 ,  G06F30/392

    Abstract: Disclosed is a computer-readable medium including a program code. The program code, when executed by a processor, causes the processor to place an electrically active pattern having a first width and a first least margin area, on a layer, to place a first dummy pattern having a second width wider than the first width and having a second least margin area, on the layer, and to place a second dummy pattern having a third width and a third least margin area, on the layer, based on whether a ratio of an area of the layer to areas of the electrically active pattern and the first dummy pattern is within a reference range.

    MEMORY COMPRESSION METHOD OF ELECTRONIC DEVICE AND APPARATUS THEREOF
    4.
    发明申请
    MEMORY COMPRESSION METHOD OF ELECTRONIC DEVICE AND APPARATUS THEREOF 审中-公开
    电子设备的记忆压缩方法及其装置

    公开(公告)号：US20150339059A1

    公开(公告)日：2015-11-26

    申请号：US14436344

    申请日：2014-10-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byoungik KANG ,  Jinyoung PARK ,  Heesub SHIN ,  Seungwook LEE

    IPC: G06F3/06

    CPC classification number: G06F3/0608 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/023 ,  G06F2212/401

    Abstract: Disclosed are a memory compression method of an electronic device and an apparatus thereof. The method for compressing memory in an electronic device may include: detecting a request for executing the first application; determining whether or not the memory compression is required for the execution of the first application; when the memory compression is required, compressing the memory corresponding to an application in progress in the background of the electronic device; and executing the first application.

    Abstract translation: 公开了一种电子设备的记忆压缩方法及其装置。 用于压缩电子设备中的存储器的方法可以包括：检测执行第一应用的请求; 确定所述存储器压缩是否需要用于执行所述第一应用; 当需要存储器压缩时，在电子设备的背景中对与应用程序相对应的存储器进行压缩; 并执行第一应用。

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220384591A1

    公开(公告)日：2022-12-01

    申请号：US17546213

    申请日：2021-12-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Doohyun LEE ,  Heonjong SHIN ,  Seon-Bae KIM ,  Minchan GWAK ,  Jinyoung PARK ,  Hyunho PARK

    IPC: H01L29/417 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786

    Abstract: A semiconductor device may include an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, a gate electrode on the channel pattern, an active contact on the source/drain pattern, a first lower interconnection line on the gate electrode, and a second lower interconnection line on the active contact and at the same level as the first lower interconnection line. The gate electrode may include an electrode body portion and an electrode protruding portion, wherein the electrode protruding portion protrudes from a top surface of the electrode body portion and is in contact with the first lower interconnection line thereon. The active contact may include a contact body portion and a contact protruding portion, wherein the contact protruding portion protrudes from a top surface of the contact body portion and is in contact with the second lower interconnection line thereon.

    ELECTRONIC DEVICE HAVING CURVED WINDOW
    7.
    发明申请
    ELECTRONIC DEVICE HAVING CURVED WINDOW 审中-公开

    公开(公告)号：US20200014781A1

    公开(公告)日：2020-01-09

    申请号：US16482401

    申请日：2018-01-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yongseok LEE ,  Minsu JUNG ,  Seungjae BAE ,  Jongkyun IM ,  Jina MOCK ,  Jinyoung PARK

    IPC: H04M1/02

    Abstract: Disclosed is an electronic device comprising: a housing including a first plate, a second plate and a lateral member for covering a gap between the first plate and the second plate; a touch screen display exposed through a first part of the first plate; a sensor exposed through the first plate; a wireless communication circuit arranged inside the housing; and a processor which is arranged inside the housing and is electrically connected to the touch screen display, the sensor and the wireless communication circuit. In addition, other embodiments are possible.

    METHOD FOR LAYOUT DESIGN AND SEMICONDUCTOR DEVICE MANUFACTURED BASED ON THE SAME
    9.
    发明申请
    METHOD FOR LAYOUT DESIGN AND SEMICONDUCTOR DEVICE MANUFACTURED BASED ON THE SAME 审中-公开

    公开(公告)号：US20190236238A1

    公开(公告)日：2019-08-01

    申请号：US16108260

    申请日：2018-08-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinyoung PARK

    IPC: G06F17/50

    Abstract: Disclosed is a computer-readable medium including a program code. The program code, when executed by a processor, causes the processor to place an electrically active pattern having a first width and a first least margin area, on a layer, to place a first dummy pattern having a second width wider than the first width and having a second least margin area, on the layer, and to place a second dummy pattern having a third width and a third least margin area, on the layer, based on whether a ratio of an area of the layer to areas of the electrically active pattern and the first dummy pattern is within a reference range.

    METHOD OF FORMING FINE PATTERN OF SEMICONDUCTOR DEVICE
    10.
    发明申请
    METHOD OF FORMING FINE PATTERN OF SEMICONDUCTOR DEVICE 有权
    形成半导体器件精细图案的方法

    公开(公告)号：US20160293445A1

    公开(公告)日：2016-10-06

    申请号：US15066492

    申请日：2016-03-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Je-Woo HAN ,  Junho YOON ,  Kyohyeok KIM ,  Dongchan KIM ,  Sungyeon KIM ,  Jaehong PARK ,  Jinyoung PARK ,  KyungYub JEON

    IPC: H01L21/311

    CPC classification number: H01L21/31144 ,  H01L21/31116 ,  H01L21/76816

    Abstract: A method of fabricating a semiconductor device is disclosed. The method may include forming an target layer on a substrate, forming a mask pattern on a target layer, performing a first process to etch the target layer and form a first sub-trench, and performing a second process to further etch the target layer and form a second sub-trench. First and second sidewall patterns may be formed on a sidewall of the mask pattern to be used as an etch mask in the first and second processes, respectively. Outer sidewalls of the first and second sidewall patterns may be formed to have different angles with respect to a top surface of the substrate.

    Abstract translation: 公开了制造半导体器件的方法。 该方法可以包括在衬底上形成目标层，在目标层上形成掩模图案，执行蚀刻目标层并形成第一子沟槽的第一工艺，以及执行第二工艺以进一步蚀刻目标层和 形成第二子沟槽。 第一和第二侧壁图案可分别形成在掩模图案的侧壁上，以分别在第一和第二工艺中用作蚀刻掩模。 第一和第二侧壁图案的外侧壁可以形成为相对于基板的顶表面具有不同的角度。

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