公开(公告)号：US20200342157A1

公开(公告)日：2020-10-29

申请号：US16794045

申请日：2020-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alexander SCHMIDT ,  Dong-Gwan SHIN ,  Anthony PAYET ,  Hyoung Soo KO ,  Seok Hoon KIM ,  Hyun-Kwan YU ,  Si Hyung LEE ,  In Kook JANG

IPC: G06F30/398 ,  H01L27/02 ,  G06F30/367

Abstract: A simulation method and system which can determine a predictable epitaxy time by accurately reflecting layout characteristics of a chip and characteristics of a source/drain formation process are provided. The simulation method includes storing a plurality of structure parameters of transistors for a semiconductor chip, the structure parameters determined by using imaging equipment, generating a first local layout which includes a first structure parameter extracted from a semiconductor device included in the first local layout, the first structure parameter being an actual parameter determined using the imaging equipment, generating second to n-th local layouts by modifying the first structure parameter included in the first local layout, wherein the second to n-th local layouts respectively have second to n-th structure parameters modified from the first structure parameter, calculating first to n-th effective density factors(EDF) respectively for the first to n-th structure parameters using a predetermined simulation of the first to n-th structure parameters, determining a first effective open silicon density for a first chip using the first to n-th effective density factors and a layout of the first chip, and calculating a first epitaxy time for the first effective open silicon density, calculating second to m-th epitaxy times for second to m-th effective open silicon densities, and performing a regression analysis of effective open silicon density versus epitaxy time based on the calculation result, where n is a natural number equal to or greater than 3, and m is a natural number equal to or greater than 3.