公开(公告)号：US20200342157A1

公开(公告)日：2020-10-29

申请号：US16794045

申请日：2020-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alexander SCHMIDT ,  Dong-Gwan SHIN ,  Anthony PAYET ,  Hyoung Soo KO ,  Seok Hoon KIM ,  Hyun-Kwan YU ,  Si Hyung LEE ,  In Kook JANG

IPC: G06F30/398 ,  H01L27/02 ,  G06F30/367

Abstract: A simulation method and system which can determine a predictable epitaxy time by accurately reflecting layout characteristics of a chip and characteristics of a source/drain formation process are provided. The simulation method includes storing a plurality of structure parameters of transistors for a semiconductor chip, the structure parameters determined by using imaging equipment, generating a first local layout which includes a first structure parameter extracted from a semiconductor device included in the first local layout, the first structure parameter being an actual parameter determined using the imaging equipment, generating second to n-th local layouts by modifying the first structure parameter included in the first local layout, wherein the second to n-th local layouts respectively have second to n-th structure parameters modified from the first structure parameter, calculating first to n-th effective density factors(EDF) respectively for the first to n-th structure parameters using a predetermined simulation of the first to n-th structure parameters, determining a first effective open silicon density for a first chip using the first to n-th effective density factors and a layout of the first chip, and calculating a first epitaxy time for the first effective open silicon density, calculating second to m-th epitaxy times for second to m-th effective open silicon densities, and performing a regression analysis of effective open silicon density versus epitaxy time based on the calculation result, where n is a natural number equal to or greater than 3, and m is a natural number equal to or greater than 3.

公开(公告)号：US20180158911A1

公开(公告)日：2018-06-07

申请号：US15887773

申请日：2018-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuichiro SASAKI ,  Bong Soo KIM ,  Tae Gon KIM ,  Yoshiya MORIYAMA ,  Seung Hyun SONG ,  Alexander SCHMIDT ,  Abraham YOO ,  Heung Soon LEE ,  Kyung In CHOI

IPC: H01L29/10 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L21/2236 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.

公开(公告)号：US20170373151A1

公开(公告)日：2017-12-28

申请号：US15424081

申请日：2017-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuichiro SASAKI ,  Bong Soo KIM ,  Tae Gon KIM ,  Yoshiya MORIYAMA ,  Seung Hyun SONG ,  Alexander SCHMIDT ,  Abraham YOO ,  Heung Soon LEE ,  Kyung In CHOI

IPC: H01L29/10 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/2236 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.