公开(公告)号：US20200342157A1

公开(公告)日：2020-10-29

申请号：US16794045

申请日：2020-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alexander SCHMIDT ,  Dong-Gwan SHIN ,  Anthony PAYET ,  Hyoung Soo KO ,  Seok Hoon KIM ,  Hyun-Kwan YU ,  Si Hyung LEE ,  In Kook JANG

IPC: G06F30/398 ,  H01L27/02 ,  G06F30/367

Abstract: A simulation method and system which can determine a predictable epitaxy time by accurately reflecting layout characteristics of a chip and characteristics of a source/drain formation process are provided. The simulation method includes storing a plurality of structure parameters of transistors for a semiconductor chip, the structure parameters determined by using imaging equipment, generating a first local layout which includes a first structure parameter extracted from a semiconductor device included in the first local layout, the first structure parameter being an actual parameter determined using the imaging equipment, generating second to n-th local layouts by modifying the first structure parameter included in the first local layout, wherein the second to n-th local layouts respectively have second to n-th structure parameters modified from the first structure parameter, calculating first to n-th effective density factors(EDF) respectively for the first to n-th structure parameters using a predetermined simulation of the first to n-th structure parameters, determining a first effective open silicon density for a first chip using the first to n-th effective density factors and a layout of the first chip, and calculating a first epitaxy time for the first effective open silicon density, calculating second to m-th epitaxy times for second to m-th effective open silicon densities, and performing a regression analysis of effective open silicon density versus epitaxy time based on the calculation result, where n is a natural number equal to or greater than 3, and m is a natural number equal to or greater than 3.

公开(公告)号：US20240038840A1

公开(公告)日：2024-02-01

申请号：US18125870

申请日：2023-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Gwan SHIN ,  Yong Hee PARK ,  Hong Seon YANG ,  Hye In CHUNG ,  Pan Kwi PARK

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/423 ,  H01L27/092

CPC classification number: H01L29/0673 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/42392 ,  H01L27/092

Abstract: A semiconductor device includes an active pattern with a first impurity having a first conductivity, first and second nanosheets on the active pattern, a gate electrode on the active pattern and surrounding each of the first and second nanosheets, a lower source/drain region on the active pattern, an uppermost surface of the lower source/drain region being lower than a lower surface of the second nanosheet, and the lower source/drain region being doped with a second impurity having the first conductivity, an upper source/drain region on the lower source/drain region, the upper source/drain region being doped with a third impurity having a second conductivity different from the first conductivity, and a gate insulation layer between the gate electrode and the lower and upper source/drain regions, the gate insulation layer being in contact with each of the lower and upper source/drain regions.

公开(公告)号：US20230231026A1

公开(公告)日：2023-07-20

申请号：US17890547

申请日：2022-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungkyu KIM ,  Yonghee PARK ,  Dong-Gwan SHIN ,  Dae Sin KIM ,  Sangyong KIM ,  Joohyung YOU

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L29/42392 ,  H01L29/6656 ,  H01L29/78696 ,  H01L29/0847

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns and extending in a first direction, and a gate insulating layer between the semiconductor patterns and the gate electrode. A first semiconductor pattern of the semiconductor patterns includes opposite side surfaces in the first direction, and bottom and top surfaces. The gate insulating layer covers the opposite side surfaces, and the bottom and top surfaces and includes a first region on one of the opposite side surfaces of the first semiconductor pattern and a second region on one of the top or bottom surfaces of the first semiconductor pattern, and a thickness of the first region may be greater than a thickness of the second region.