公开(公告)号：US20170277125A1

公开(公告)日：2017-09-28

申请号：US15373008

申请日：2016-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wook-Dam JUNG ,  Yongcheon KANG ,  Dong-Jin YIM ,  Hyun-Seok CHANG ,  Sanghyuck JUNG ,  Jeongeun KIM ,  Byoung-Uk YOON

IPC: G04B19/28 ,  G04G21/00

CPC classification number: G04B19/283 ,  G04C3/004 ,  G04G17/04 ,  G04G21/00

Abstract: Various example embodiments of the present disclosure provide an electronic device including: a housing including a substantially circular opening and a first surface facing in a first direction; a wearing structure configured to enable the electronic device to be removably worn on a part of a human body and connected to the housing; a display disposed in the opening; an annulus installed on the first surface and configured to be rotatable along a periphery of the opining, the annulus including a second surface facing a second direction opposite the first direction; at least one spacer interposed between a part of the first surface and the second surface of the annulus; and a circuit configured to detect a rotation of the annular member and to change the display at least in part based on the rotation.

公开(公告)号：US20220406808A1

公开(公告)日：2022-12-22

申请号：US17724002

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin LEE ,  Junhee LIM ,  Hakseon KIM ,  Nakjin SON ,  Jeongeun KIM ,  Juseong MIN ,  Changheon LEE

IPC: H01L27/11573 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

Abstract: A semiconductor device includes a lower level layer including a peripheral circuit; and an upper level layer provided on the lower level layer, the upper level layer including a vertically-extended memory cell string, wherein the lower level layer includes a first substrate; a device isolation layer defining a first active region of the first substrate; and a first gate structure including a first gate insulating pattern, a first conductive pattern, a first metal pattern, and a first capping pattern, which are sequentially stacked on the first active region, wherein the first conductive pattern comprises a doped semiconductor material, and the device isolation layer covers a first side surface of the first conductive pattern, and the first metal pattern includes a first body portion on the first conductive pattern.

公开(公告)号：US20210399010A1

公开(公告)日：2021-12-23

申请号：US17204010

申请日：2021-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Youngjin KWON ,  Jeongeun KIM ,  Byunggon PARK ,  Sungwon CHO

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11595 ,  H01L23/528

Abstract: A memory device includes a lower structure, a stacked structure on the lower structure, the stacked structure including horizontal layers and interlayer insulating layers alternately stacked in a vertical direction, and each of the horizontal layers including a gate electrode, a vertical structure penetrating through the stacked structure in the vertical direction, the vertical structure having a core region, a pad pattern with a pad metal pattern on the core region, a dielectric structure including a first portion facing a side surface of the core region, a second portion facing at least a portion of a side surface of the pad metal pattern, and a data storage layer, and a channel layer between the dielectric structure and the core region, a contact structure on the vertical structure, and a conductive line on the contact structure.