公开(公告)号：US20240162225A1

公开(公告)日：2024-05-16

申请号：US18318854

申请日：2023-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juseong MIN ,  Jae-Bok Baek ,  Taekkyu Yoon ,  Seungwook Choi ,  Jeehoon Han ,  Taeyoon Hong

IPC: H01L27/08 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L27/0802 ,  H01L21/30604 ,  H01L21/308 ,  H01L28/20

Abstract: A semiconductor device includes an active pattern having sharp corners. The semiconductor device includes a peripheral circuit including a substrate, a resistor device in the substrate, and an active pattern on the substrate. When viewed in a plan view, the active pattern includes corners in a serpentine shape, and first and second shapes of the corners are different from each other.

公开(公告)号：US20220406808A1

公开(公告)日：2022-12-22

申请号：US17724002

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin LEE ,  Junhee LIM ,  Hakseon KIM ,  Nakjin SON ,  Jeongeun KIM ,  Juseong MIN ,  Changheon LEE

IPC: H01L27/11573 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

Abstract: A semiconductor device includes a lower level layer including a peripheral circuit; and an upper level layer provided on the lower level layer, the upper level layer including a vertically-extended memory cell string, wherein the lower level layer includes a first substrate; a device isolation layer defining a first active region of the first substrate; and a first gate structure including a first gate insulating pattern, a first conductive pattern, a first metal pattern, and a first capping pattern, which are sequentially stacked on the first active region, wherein the first conductive pattern comprises a doped semiconductor material, and the device isolation layer covers a first side surface of the first conductive pattern, and the first metal pattern includes a first body portion on the first conductive pattern.

公开(公告)号：US20240113160A1

公开(公告)日：2024-04-04

申请号：US18303205

申请日：2023-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juseong MIN ,  Kyeonghoon PARK ,  Jae-Bok BAEK ,  Donghyuck JANG ,  Jeehoon HAN ,  Taeyoon HONG

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/423

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L29/4236

Abstract: A semiconductor device include a substrate including a plurality of protrusions protruding from an upper surface thereof and arranged two-dimensionally in a first direction and a second direction intersecting each other, a first trench provided between the protrusions in the first direction, and a second trench provided between the protrusions in the second direction, a first device isolation layer filling the first trench, gate patterns disposed on the protrusions in the second direction, upper surfaces of the protrusions exposed at both sides of the gate patterns, respectively, and a second device isolation layer filling a space between the gate patterns in the second direction and the second trench, and each of the gate patterns has a first sidewall adjacent to the second trench and aligned with an inner wall of the second trench.

公开(公告)号：US20240032298A1

公开(公告)日：2024-01-25

申请号：US18177335

申请日：2023-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyeonghoon PARK ,  Juseong MIN ,  Jaebok BAEK ,  Donghyuck JANG ,  Sanghun CHUN ,  Jeehoon HAN ,  Taeyoon HONG

IPC: H10B43/40 ,  H10B43/10 ,  H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  G11C5/06

CPC classification number: H10B43/40 ,  H10B43/10 ,  H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  G11C5/06

Abstract: A semiconductor device includes a peripheral circuit structure including circuits, wiring layers, and via contacts, a plate common source line covering the peripheral circuit structure, an insulating plug passing through the plate common source line, a lateral insulating spacer between the peripheral circuit structure and the plate common source line, a memory stack structure including gate lines on the plate common source line, a through contact passing through at least one of the gate lines and the insulating plug, the through contact being connected to a first via contact of the via contacts, and a source line contact passing through the lateral insulating spacer, the source line contact being between a second via contact of the via contacts and the plate common source line, wherein a width of the first via contact is greater than a width of the insulating plug in a lateral direction.