公开(公告)号：US20250040154A1

公开(公告)日：2025-01-30

申请号：US18624857

申请日：2024-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hakseon KIM ,  Dongjin LEE ,  Jaeduk LEE ,  Kangoh YUN

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a peripheral circuit structure; and a cell structure on the peripheral circuit structure, wherein the peripheral circuit structure comprises: a substrate comprising a cell region, a connection region adjacent to the cell region, and a pad region extending around the cell region and the connection region; a first connection structure between the substrate and the cell structure; a first peripheral circuit transistor in the cell region and/or the connection region; and a second peripheral circuit transistor in the pad region, wherein the first connection structure includes a first wiring structure and a dummy structure, the first wiring structure is electrically connected to the first peripheral circuit transistor and/or the second peripheral circuit transistor, and the dummy structure is not directly connected to the first peripheral circuit transistor.

公开(公告)号：US20240324194A1

公开(公告)日：2024-09-26

申请号：US18602778

申请日：2024-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjin LEE ,  Junhee LIM ,  Hakseon KIM ,  Kangoh YUN ,  Sohyun LEE

IPC: H10B41/35 ,  G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B80/00

CPC classification number: H10B41/35 ,  G11C16/0483 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B80/00 ,  H01L2225/06506

Abstract: An integrated circuit device includes a substrate including an active region including a central active region, base active regions and extended active regions integrated together and defined by a device isolation film. A drain region is located in the central active region, and source regions are respectively located in the base active regions. The base active regions are spaced apart from each other in different diagonal directions with respect to the central active region in a plan view. The extended active regions each have an L-shape, connect the central active region and the base active regions, and are spaced apart from each other. Gate structures that respectively cross the base active regions and are spaced apart from each other on the substrate. The central active region, the extended active regions, the base active regions, and the gate structures configure pass transistors, and the pass transistors share the drain region.

公开(公告)号：US20240179899A1

公开(公告)日：2024-05-30

申请号：US18514158

申请日：2023-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseon KIM ,  Nakjin SON ,  Dongjin LEE ,  Junhee LIM ,  Seongsu KIM ,  Hanmin CHO ,  Chiwoong HAM

IPC: H10B41/41 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/41 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A NAND flash device may include a peripheral circuit including a transistor, a substrate, and a device isolation region defining an active region of the substrate. The transistor may include a first gate structure on the active region. The transistor may include source and drain regions extending in a first direction in the active region on both sides of the first gate structure, which may include a first lightly-doped source and drain region adjacent to the first gate structure and a second lightly-doped source and drain region integrally connected thereto. The second lightly-doped source and drain region may be arranged farther from the first gate structure than the first lightly-doped source and drain region. The second lightly-doped source and drain region may have a smaller width in the second direction than a width of the first lightly-doped source and drain region in the second direction.

公开(公告)号：US20220406808A1

公开(公告)日：2022-12-22

申请号：US17724002

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin LEE ,  Junhee LIM ,  Hakseon KIM ,  Nakjin SON ,  Jeongeun KIM ,  Juseong MIN ,  Changheon LEE

IPC: H01L27/11573 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

Abstract: A semiconductor device includes a lower level layer including a peripheral circuit; and an upper level layer provided on the lower level layer, the upper level layer including a vertically-extended memory cell string, wherein the lower level layer includes a first substrate; a device isolation layer defining a first active region of the first substrate; and a first gate structure including a first gate insulating pattern, a first conductive pattern, a first metal pattern, and a first capping pattern, which are sequentially stacked on the first active region, wherein the first conductive pattern comprises a doped semiconductor material, and the device isolation layer covers a first side surface of the first conductive pattern, and the first metal pattern includes a first body portion on the first conductive pattern.

公开(公告)号：US20230389322A1

公开(公告)日：2023-11-30

申请号：US18133278

申请日：2023-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjin LEE ,  Junhee LIM ,  Donghoon KWON ,  Hakseon KIM ,  Nakjin SON ,  Yanghee LEE ,  Juhyun LEE

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC classification number: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor device includes a peripheral circuit region including a first substrate, circuit elements on the first substrate, a first interconnection structure electrically connected to the circuit elements, first to fourth peripheral region insulating layer; and a memory cell region including a second substrate on the peripheral circuit region and having a first region and a second region, gate electrodes stacked on the first region, a cell region insulating layer covering the gate electrodes, channel structures passing through the gate electrodes, and a second interconnection structure electrically connected to the gate electrodes and the channel structures. The peripheral circuit region further includes first to fourth lower protective layers, at least one of the first, second, third and fourth lower protective layers includes a hydrogen diffusion barrier layer configured to inhibit a hydrogen element included in the cell region insulating layer from diffusing to the circuit elements, and including aluminum oxide.

公开(公告)号：US20210028283A1

公开(公告)日：2021-01-28

申请号：US16822389

申请日：2020-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkweon BAEK ,  Taeyoung KIM ,  Hakseon KIM ,  Kangoh YUN ,  Changhoon JEON ,  Junhee LIM

IPC: H01L29/10 ,  H01L29/423

Abstract: A semiconductor device includes a gate structure disposed on a substrate. The gate structure has a first sidewall and a second sidewall facing the first sidewall. A first impurity region is disposed within an upper portion of the substrate. The first impurity region is spaced apart from the first sidewall. A third impurity region is within the upper portion of the substrate. The third impurity region is spaced apart from the second sidewall. A first trench is disposed within the substrate between the first sidewall and the first impurity region. The first trench is spaced apart from the first sidewall. A first barrier insulation pattern is disposed within the first trench.