公开(公告)号：US20250133793A1

公开(公告)日：2025-04-24

申请号：US18663416

申请日：2024-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryeol YOO ,  Jaejun KIM ,  Ingyu JANG ,  Gwangjun KIM ,  Sunghwan KIM ,  Jiwon JEONG ,  Jeongsang PYO

IPC: H01L29/36 ,  H01L29/167

Abstract: A semiconductor device includes a substrate; an active pattern extending on the substrate in a first direction; a plurality of channel layers on the active pattern and spaced apart from each other in a vertical direction; a gate structure crossing the active pattern, the gate structure surrounding the plurality of channel layers and extending in a second direction orthogonal to the first direction; and source/drain patterns on a region of the active pattern on both sides of the gate structure, and having a semiconductor liner layer connected to each of side surfaces of the plurality of channel layers, and a semiconductor filling layer on the semiconductor liner layer. The semiconductor liner layer includes silicon-germanium (SiGe) doped with a first conductivity-type impurity. The semiconductor filling layer includes an epitaxial layer having a germanium (Ge) concentration higher than that of the semiconductor liner layer, and the epitaxial layer is doped with Ga.