公开(公告)号：US20220115500A1

公开(公告)日：2022-04-14

申请号：US17560865

申请日：2021-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunhye CHOI ,  Seung Mo KANG ,  Jungtaek KIM ,  Moon Seung YANG ,  Jongryeol YOO

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08

Abstract: A semiconductor device including an insulating layer on a substrate; channel semiconductor patterns stacked on the insulating layer and vertically spaced apart from each other; a gate electrode crossing the channel semiconductor patterns; source/drain regions respectively at both sides of the gate electrode and connected to each other through the channel semiconductor patterns, the source/drain regions having concave bottom surfaces; and air gaps between the insulating layer and the bottom surfaces of the source/drain regions.

公开(公告)号：US20250133793A1

公开(公告)日：2025-04-24

申请号：US18663416

申请日：2024-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryeol YOO ,  Jaejun KIM ,  Ingyu JANG ,  Gwangjun KIM ,  Sunghwan KIM ,  Jiwon JEONG ,  Jeongsang PYO

IPC: H01L29/36 ,  H01L29/167

Abstract: A semiconductor device includes a substrate; an active pattern extending on the substrate in a first direction; a plurality of channel layers on the active pattern and spaced apart from each other in a vertical direction; a gate structure crossing the active pattern, the gate structure surrounding the plurality of channel layers and extending in a second direction orthogonal to the first direction; and source/drain patterns on a region of the active pattern on both sides of the gate structure, and having a semiconductor liner layer connected to each of side surfaces of the plurality of channel layers, and a semiconductor filling layer on the semiconductor liner layer. The semiconductor liner layer includes silicon-germanium (SiGe) doped with a first conductivity-type impurity. The semiconductor filling layer includes an epitaxial layer having a germanium (Ge) concentration higher than that of the semiconductor liner layer, and the epitaxial layer is doped with Ga.

公开(公告)号：US20240274665A1

公开(公告)日：2024-08-15

申请号：US18462851

申请日：2023-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryeol YOO

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor device may include a substrate, a channel pattern on the substrate, a source/drain pattern, an interlayer insulating pattern on the source/drain pattern, and an active contact penetrating the interlayer insulating layer and being electrically connected to the source/drain pattern. The channel pattern may include a plurality of semiconductor patterns. The plurality of semiconductor patterns may be vertically stacked and spaced apart from each other. A lowermost one of the plurality of semiconductor patterns may be a first semiconductor pattern. The source/drain pattern may be connected to the plurality of semiconductor patterns. A level of a bottommost surface of the active contact may be lower than a top surface of the first semiconductor pattern.

公开(公告)号：US20220149210A1

公开(公告)日：2022-05-12

申请号：US17584545

申请日：2022-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Mo KANG ,  Moon Seung YANG ,  Jongryeol YOO ,  Sihyung LEE ,  Sunguk JANG ,  Eunhye CHOI

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311

Abstract: A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.

公开(公告)号：US20190139811A1

公开(公告)日：2019-05-09

申请号：US15869718

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Seokhoon KIM ,  Seung Hun LEE ,  Yang XU ,  Jeongho YOO ,  Jongryeol YOO ,  Youngdae CHO

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/423 ,  H01L29/165 ,  H01L21/02 ,  H01L21/225

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active tin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin

公开(公告)号：US20240282708A1

公开(公告)日：2024-08-22

申请号：US18464539

申请日：2023-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryeol YOO

IPC: H01L23/528 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L23/5286 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor device may include a substrate, a lower power line buried in a lower portion of the substrate, a source/drain pattern on the substrate, an interlayer insulating layer on the source/drain pattern, and a back-side contact penetrating the substrate and electrically connecting the lower power line to the source/drain pattern. The back-side contact may penetrate the source/drain pattern and may include a first surface in contact with the interlayer insulating layer.

公开(公告)号：US20200075764A1

公开(公告)日：2020-03-05

申请号：US16412796

申请日：2019-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunguk JANG ,  Sujin JUNG ,  Jinyeong JOE ,  Jeongho YOO ,  Seung Hun LEE ,  Jongryeol YOO

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L27/088

Abstract: A semiconductor device includes a first active fin protruding from a substrate, a first gate pattern covering a side surface and a top surface of the first active fin, and first source/drain patterns at opposite sides of the first gate pattern, each of the first source/drain patterns including a first lower side and a second lower side spaced apart from each other, a first upper side extended from the first lower side, a second upper side extended from the second lower side. The first lower side may be inclined at a first angle relative to a top surface of the substrate, the second upper side may be inclined at a second angle relative to the top surface of the substrate, and the first angle may be greater than the second angle.

公开(公告)号：US20160056269A1

公开(公告)日：2016-02-25

申请号：US14749037

申请日：2015-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Jung LEE ,  Bonyoung KOO ,  Sunjung KIM ,  Jongryeol YOO ,  Seung Hun LEE ,  Poren TANG

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/66795 ,  H01L21/3085 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823807

Abstract: A method of fabricating a semiconductor device includes forming a channel layer on a substrate, forming a sacrificial layer on the channel layer, forming a hardmask pattern on the sacrificial layer, and performing a patterning process using the hardmask pattern as an etch mask to form a channel portion with an exposed top surface. The channel and sacrificial layers may be formed of silicon germanium, and the sacrificial layer may have a germanium content higher than that of the channel layer.

Abstract translation: 制造半导体器件的方法包括在衬底上形成沟道层，在沟道层上形成牺牲层，在牺牲层上形成硬掩模图案，并使用硬掩模图案作为蚀刻掩模进行图案化处理，形成 通道部分具有​​暴露的顶表面。 通道和牺牲层可由硅锗形成，并且牺牲层的锗含量可高于沟道层的锗含量。

公开(公告)号：US20210143049A1

公开(公告)日：2021-05-13

申请号：US17137485

申请日：2020-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Seokhoon KIM ,  Seung Hun LEE ,  Yang XU ,  Jeongho YOO ,  Jongryeol YOO ,  Youngdae CHO

IPC: H01L21/762 ,  H01L21/225 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active fin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin

公开(公告)号：US20200381564A1

公开(公告)日：2020-12-03

申请号：US16774653

申请日：2020-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Mo KANG ,  Moon Seung YANG ,  Jongryeol YOO ,  Sihyung LEE ,  Sunguk JANG ,  Eunhye CHOI

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/08

Abstract: A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.