公开(公告)号：US20170200727A1

公开(公告)日：2017-07-13

申请号：US15399243

申请日：2017-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon YOON ,  Hyun-Min CHOI

IPC: H01L27/112 ,  H01L23/525

Abstract: A semiconductor device is disclosed. The semiconductor device including writing and reading gate electrodes respectively on first and second active regions on a substrate, a first gate insulation pattern between the first active region and the writing gate electrode, a second gate insulation pattern between the second active region and the reading gate electrode, first and second source/drain junction regions in the first and second active regions at sides of the writing and reading gate electrodes, and a connection structure that connects the first and second source/drain junction regions. The first active region has the same conductivity type as the source/drain junction regions. The second active region has a different conductivity type from the source/drain junction regions.

公开(公告)号：US20150123209A1

公开(公告)日：2015-05-07

申请号：US14532152

申请日：2014-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min CHOI ,  Shigenobu MAEDA ,  Jihoon YOON ,  SUNGMAN LIM

IPC: H01L27/112 ,  H01L29/423 ,  H01L23/525 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/11206 ,  H01L23/5226 ,  H01L23/5252 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/42372 ,  H01L29/785 ,  H01L29/7851

Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line. The first conductive line forms a gate electrode of an anti-fuse that may be applied with a write voltage.

Abstract translation: 本发明构思提供半导体器件及其制造方法。 一个半导体器件包括衬底，设置在衬底上的器件隔离层，由器件隔离层限定并且具有高于器件隔离层的顶表面的顶表面的翅片型有源图案，设置在器件隔离层上的第一导电线 翅片型有源图案的边缘部分和与鳍式有源图案的边缘部分相邻的器件隔离层，以及设置在鳍式有源图案和第一导电线之间的绝缘薄层。 第一导线形成可以施加写入电压的反熔丝的栅电极。

公开(公告)号：US20170047335A1

公开(公告)日：2017-02-16

申请号：US15334411

申请日：2016-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Min CHOI ,  Shigenobu MAEDA ,  Jihoon YOON ,  SUNGMAN LIM

IPC: H01L27/112 ,  H01L23/525 ,  H01L23/522 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/11206 ,  H01L23/5226 ,  H01L23/5252 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/42372 ,  H01L29/785 ,  H01L29/7851

Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line. The first conductive line forms a gate electrode of an anti-fuse that may be applied with a write voltage.

Abstract translation: 本发明构思提供半导体器件及其制造方法。 一个半导体器件包括衬底，设置在衬底上的器件隔离层，由器件隔离层限定并且具有高于器件隔离层的顶表面的顶表面的翅片型有源图案，设置在器件隔离层上的第一导电线 翅片型有源图案的边缘部分和与鳍式有源图案的边缘部分相邻的器件隔离层，以及设置在鳍式有源图案和第一导电线之间的绝缘薄层。 第一导线形成可以施加写入电压的反熔丝的栅电极。