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1.发明申请SEMICONDUCTOR DEVICES INCLUDING ACTIVE FINS AND METHODS OF MANUFACTURING THE SAME 有权包括有源FINS的半导体器件及其制造方法公开(公告)号：US20160293697A1
公开(公告)日：2016-10-06
申请号：US15058466
申请日：2016-03-02
发明人： Dong-Woo KIM , Shigenobu MAEDA , Young-Moon CHOI , Yong-Bum KWON , Chang-Woo SOHN , Do-Sun LEE
IPC分类号： H01L29/06 , H01L27/088 , H01L29/161 , H01L23/528 , H01L29/16 , H01L29/78 , H01L29/08
CPC分类号： H01L21/823431 , H01L21/823418 , H01L21/823814 , H01L21/823821 , H01L27/0886 , H01L27/0924 , H01L29/0653 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/66545 , H01L29/6656 , H01L29/785
摘要： Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins in a second direction, and a first source/drain layer on first active fins of the active fins adjacent the gate structure. At least one of two opposing sidewalls of a cross-section of the first source/drain layer taken along the second direction may include a curved portion having a slope with respect to an upper surface of the substrate. The slope may decrease from a bottom toward a top thereof.
摘要翻译： 半导体器件可以包括多个有源散热片，每个有源散热片各自在衬底上沿第一方向延伸，栅极结构在第二方向上在有源鳍片上延伸;以及第一源/漏极层，位于邻近栅极的有源散热片的第一有源散热片上 结构体。 沿着第二方向截取的第一源/漏层的横截面的两个相对的侧壁中的至少一个可以包括相对于衬底的上表面具有斜率的弯曲部分。 斜面可能从底部向其顶部减小。
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公开(公告)号：US20240213317A1
公开(公告)日：2024-06-27
申请号：US18596461
申请日：2024-03-05
发明人： Shigenobu MAEDA , Hee-Soo Kang , Sang-Pil Sim , Soo-Hun Hong
IPC分类号： H01L29/06 , B82Y10/00 , H01L21/8234 , H01L21/84 , H01L27/088 , H01L27/12 , H01L29/08 , H01L29/10 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/417 , H01L29/49 , H01L29/51 , H01L29/66 , H01L29/775 , H01L29/78
CPC分类号： H01L29/0692 , B82Y10/00 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/1037 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41791 , H01L29/4966 , H01L29/517 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L29/775
摘要： A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.
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公开(公告)号：US20210327366A1
公开(公告)日：2021-10-21
申请号：US17215230
申请日：2021-03-29
发明人： Shigenobu MAEDA , Dong-Il PARK
IPC分类号： G09G3/3291
摘要： A display driver integrated circuit (IC) is provided. The display driver IC includes a shift register configured to output a digital signal, and a digital-analog converter configured to receive the digital signal and generate a data voltage corresponding to the digital signal, wherein the digital-analog converter includes a delta-sigma modulator configured to output a modulated signal by receiving the digital signal and a first voltage, and performing delta-sigma modulation on the digital signal using the first voltage, and a level shifter configured to receive the modulated signal and a second voltage higher than the first voltage, and amplify the modulated signal using the second voltage.
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公开(公告)号：US20150123209A1
公开(公告)日：2015-05-07
申请号：US14532152
申请日：2014-11-04
发明人： Hyun-Min CHOI , Shigenobu MAEDA , Jihoon YOON , SUNGMAN LIM
IPC分类号： H01L27/112 , H01L29/423 , H01L23/525 , H01L29/06 , H01L29/78
CPC分类号： H01L27/11206 , H01L23/5226 , H01L23/5252 , H01L27/0207 , H01L29/0649 , H01L29/0653 , H01L29/42372 , H01L29/785 , H01L29/7851
摘要： The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line. The first conductive line forms a gate electrode of an anti-fuse that may be applied with a write voltage.
摘要翻译： 本发明构思提供半导体器件及其制造方法。 一个半导体器件包括衬底，设置在衬底上的器件隔离层，由器件隔离层限定并且具有高于器件隔离层的顶表面的顶表面的翅片型有源图案，设置在器件隔离层上的第一导电线 翅片型有源图案的边缘部分和与鳍式有源图案的边缘部分相邻的器件隔离层，以及设置在鳍式有源图案和第一导电线之间的绝缘薄层。 第一导线形成可以施加写入电压的反熔丝的栅电极。
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公开(公告)号：US20150076655A1
公开(公告)日：2015-03-19
申请号：US14261505
申请日：2014-04-25
发明人： Hyun-Min Choi , Shigenobu MAEDA
IPC分类号： H01L23/62 , H01L23/498 , H01L21/768
CPC分类号： H01L23/5256 , H01L21/76886 , H01L23/49827 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L23/62 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line.
摘要翻译： 提供熔丝结构及其吹塑方法。 熔丝结构包括在基板上的导电线，导电线上彼此间隔开的第一和第二通孔，电连接到第一通孔的阴极电极线，电连接到第一通孔的阳极电极线 第二通孔和与阴极和阳极电极线中的至少一个相邻并且与导电线电绝缘的虚设图案。
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公开(公告)号：US20210313430A1
公开(公告)日：2021-10-07
申请号：US17352989
申请日：2021-06-21
发明人： Shigenobu MAEDA , Seunghan SEO , Yeohyun SUNG
IPC分类号： H01L29/16 , H01L29/165 , H01L29/267 , H01L29/778 , H01L29/786 , H01L29/24 , H01L29/66 , H01L29/04 , H01L29/08 , H01L29/10 , H01L29/20 , H01L29/22 , H01L29/78
摘要： A semiconductor device is provided and includes a substrate and a stack on the substrate. The stack includes plural active layers that are vertically stacked and spaced apart from each other, and plural gate electrodes that are on the active layers, respectively, and vertically stacked. Each active layer includes a channel layer under a corresponding one of the gate electrodes, and a source/drain layer disposed at a side of the channel layer and electrically connected to the channel layer. The channel layer is made of a two-dimensional atomic layer of a first material.
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公开(公告)号：US20190355719A1
公开(公告)日：2019-11-21
申请号：US16372166
申请日：2019-04-01
发明人： Shigenobu MAEDA , Sung Chul PARK , Chul Hong PARK , Yoshinao HARADA , Sung Min KANG , Ji Wook KWON , Ha-Young KIM , Yuichi HIRANO
IPC分类号： H01L27/088 , H01L29/06 , H01L29/40
摘要： A semiconductor device includes first to fourth cells sequentially disposed on a substrate, first to third diffusion break structures, a first fin structure configured to protrude from the substrate, the first fin structure comprising first to fourth fins separated from each other by the first to third diffusion break structures, a second fin structure configured to protrude from the substrate, to be spaced apart from the first fin structure, the second fin structure comprising fifth to eighth fins separated from each other by the first to third diffusion break structures, the first to fourth gate electrodes being disposed in the first to fourth cells, respectively, and the number of fins in one cell of the first to fourth cells is different from the number of fins in an other cell of the first to fourth cells.
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公开(公告)号：US20170162654A1
公开(公告)日：2017-06-08
申请号：US15340199
申请日：2016-11-01
发明人： Shigenobu MAEDA , Seunghan SEO , Yeohyun SUNG
CPC分类号： H01L29/1606 , H01L29/04 , H01L29/0847 , H01L29/1037 , H01L29/1054 , H01L29/165 , H01L29/2003 , H01L29/22 , H01L29/24 , H01L29/267 , H01L29/517 , H01L29/778 , H01L29/78 , H01L29/786
摘要： A field effect transistor and a semiconductor device including the same are provided. The semiconductor device may include a channel layer, which is provided on a substrate and includes a two-dimensional atomic layer made of a first material, and a source/drain layer, which is provided on the substrate and includes a second material. The first material may be one of phosphorus allotropes, the second material may be one of carbon allotropes, and the channel layer and the source/drain layer may be connected to each other by covalent bonds between the first and second materials.
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公开(公告)号：US20160118342A1
公开(公告)日：2016-04-28
申请号：US14986872
申请日：2016-01-04
发明人： Hyun-Min CHOI , Shigenobu MAEDA
IPC分类号： H01L23/525 , H01L27/112 , H01L23/532 , H01L23/522 , H01L23/528
CPC分类号： H01L23/5256 , H01L21/76886 , H01L23/49827 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L23/62 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line.
摘要翻译： 提供熔丝结构及其吹塑方法。 熔丝结构包括在基板上的导电线，导电线上彼此间隔开的第一和第二通孔，电连接到第一通孔的阴极电极线，电连接到第一通孔的阳极电极线 第二通孔和与阴极和阳极电极线中的至少一个相邻并且与导电线电绝缘的虚设图案。
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公开(公告)号：US20160093398A1
公开(公告)日：2016-03-31
申请号：US14753620
申请日：2015-06-29
发明人： Hyun-Min CHOI , Shigenobu MAEDA , Ji-Hoon YOON
CPC分类号： G11C13/004 , G11C11/5685 , G11C11/5692 , G11C13/0007 , G11C13/0069 , G11C17/165 , G11C17/18 , G11C2213/53
摘要： A memory device may include nonvolatile memory cells. A first memory cell of the nonvolatile memory cells may have a first resistance value in a first state and a second memory cell of the nonvolatile memory cells may have a second resistance value less than the first resistance value in a second state. A third memory cell of the nonvolatile memory cells may have a third resistance value less than the first resistance value and greater than the second resistance value in a third state, and a fourth memory cell of the nonvolatile memory cells may have a fourth resistance value less than the third resistance value and greater than the second resistance value in a fourth state.
摘要翻译： 存储器件可以包括非易失性存储器单元。 非易失性存储器单元的第一存储单元可以具有第一状态的第一电阻值，并且非易失性存储单元的第二存储单元可具有小于第二状态的第一电阻值的第二电阻值。 非易失性存储单元的第三存储单元可具有小于第一电阻值的第三电阻值并且大于第三状态中的第二电阻值，并且非易失性存储单元的第四存储单元可具有较小的第四电阻值 大于第四电阻值且大于第四电阻值。
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