公开(公告)号：US20240365528A1

公开(公告)日：2024-10-31

申请号：US18643224

申请日：2024-04-23

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Changhoon SUNG ,  Hyojin Cho ,  Hoyoung Tang ,  Taehyung Kim ,  Eojin Lee

IPC分类号： H10B10/00 ,  G11C5/06 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC分类号： H10B10/125 ,  G11C5/063 ,  H01L23/5283 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

摘要： An integrated circuit is provided and includes a memory cell array, a plurality of gate electrodes extending in a first direction above a substrate, a plurality of word lines extending in the first direction above the substrate, a plurality of bit lines extending below the substrate in a second direction intersecting the first direction, and a plurality of first contacts passing through the substrate in a vertical direction and respectively connected to the plurality of bit lines.

公开(公告)号：US20240363707A1

公开(公告)日：2024-10-31

申请号：US18769182

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Wen HUANG ,  Chung-Ting KO ,  Hong-Hsien KE ,  Chia-Hui LIN ,  Tai-Chun HUANG

IPC分类号： H01L29/417 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L21/02063 ,  H01L21/0217 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02343 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848

摘要： A semiconductor device is provided. The semiconductor device includes a source/drain structure, a contact structure, a glue layer, a barrier layer, and a silicide layer. The contact structure is over the source/drain structure. The glue layer surrounds the contact structure. The barrier layer is formed on at least a portion of a sidewall surface of the contact structure. The silicide layer is between the source/drain structure and the contact structure, and the silicide layer is in direct contact with the glue layer. The bottom surface of the glue layer is lower than the top surface of the source/drain structure and the bottom surface of the barrier layer.

公开(公告)号：US20240363531A1

公开(公告)日：2024-10-31

申请号：US18626935

申请日：2024-04-04

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Soyeon Kim ,  Hoyoung Tang ,  Taehyung Kim

IPC分类号： H01L23/528 ,  G11C5/06 ,  G11C11/419 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H10B10/00

CPC分类号： H01L23/5283 ,  G11C5/063 ,  G11C11/419 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696 ,  H10B10/125

摘要： Provided is an integrated circuit including a cell array disposed on a substrate and including a plurality of bit cells, a row decoder including a plurality of word line drivers each providing a plurality of word line signals to the cell array, a backside wiring layer disposed on a back side of the substrate to overlap the row decoder and providing power to the plurality of word line drivers, and a plurality of backside contacts between the row decoder and the backside wiring layer. Each of the plurality of backside contacts extends from a source of at least one transistor included in each of the plurality of word line drivers to the backside wiring layer.

公开(公告)号：US20240363437A1

公开(公告)日：2024-10-31

申请号：US18770367

申请日：2024-07-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shahaji B. MORE

IPC分类号： H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/04 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823814 ,  H01L21/02609 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

摘要： The present disclosure describes a method of forming a semiconductor device having epitaxial structures with optimized dimensions. The method includes forming first and second fin structures on a substrate, forming a spacer layer on the first and second fin structures, forming a first spacer structure adjacent to the first fin structure, and forming a first epitaxial structure adjacent to the first spacer structure. The first and second fin structures are separated by an isolation layer. The first spacer structure has a first height above the isolation layer. The method further includes forming a second spacer structure adjacent to the second fin structure and forming a second epitaxial structure adjacent to the second spacer structure. The second spacer structure has a second height above the isolation layer greater than the first height. The second epitaxial structure includes a type of dopant different from the first epitaxial structure.

公开(公告)号：US20240363404A1

公开(公告)日：2024-10-31

申请号：US18767722

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Cheng CHEN ,  Tang-Kuei CHANG ,  Yee-Chia YEO ,  Huicheng CHANG ,  Wei-Wei LIANG ,  Ji CUI ,  Fu-Ming HUANG ,  Kei-Wei CHEN ,  Liang-Yin CHEN

IPC分类号： H01L21/768 ,  H01L21/321 ,  H01L23/522 ,  H01L23/532 ,  H01L23/535 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78

CPC分类号： H01L21/76859 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/7851

摘要： The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.

公开(公告)号：US20240363352A1

公开(公告)日：2024-10-31

申请号：US18767601

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chandrashekhar Prakash SAVANT ,  Tien-Wei YU ,  Chia-Ming TSAI

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7851

摘要： The present disclosure describes method to form a semiconductor device with a diffusion barrier layer. The method includes forming a gate dielectric layer on a fin structure, forming a work function stack on the gate dielectric layer, reducing a carbon concentration in the work function stack, forming a barrier layer on the work function stack, and forming a metal layer over the barrier layer. The barrier layer blocks a diffusion of impurities into the work function stack, the gate dielectric layer, and the fin structure.

公开(公告)号：US12132113B2

公开(公告)日：2024-10-29

申请号：US18204469

申请日：2023-06-01

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sung Uk Jang ,  Young Dae Cho ,  Ki Hwan Kim ,  Su Jin Jung

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L29/7851 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/78696

摘要： A semiconductor device and a method for making a semiconductor device. The semiconductor device includes an active region on a substrate, channel layers on the active region and spaced apart vertically, a gate structure intersecting the active region and the channel layers, the gate structure surrounding the channel layers, and a source/drain region on the active region at a side of the gate structure, the source/drain region contacting the channel layers and including first epitaxial layers having a first composition and including first layers on side surfaces of the channel layers and a second layer on the active region at a lower end of the source/drain region, and a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer being between the first epitaxial layers in the first direction and being between the first epitaxial layers vertically.

公开(公告)号：US12131945B2

公开(公告)日：2024-10-29

申请号：US17580725

申请日：2022-01-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Lien Huang

IPC分类号： H01L21/768 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/76877 ,  H01L21/76802 ,  H01L21/76831 ,  H01L29/66795 ,  H01L29/7851

摘要： The method for forming a semiconductor device includes forming a gate structure over a substrate; forming a plurality of source/drain structures in the substrate and on opposite sides of the gate structure; forming a source/drain contact on one of the plurality of source/drain structures; etching back the source/drain contact; forming a protective structure over the etched back source/drain contact; forming a dielectric layer over the gate structure and the protective structure; etching the dielectric layer to form an opening that exposes the gate structure and the protective structure; selectively depositing a capping material on the protective structure; after selectively depositing the capping material, forming a gate contact in the opening.

公开(公告)号：US12131943B2

公开(公告)日：2024-10-29

申请号：US18359412

申请日：2023-07-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Sai-Hooi Yeong ,  Yen-Chieh Huang

IPC分类号： H01L29/66 ,  H01L21/764 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L21/764 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

摘要： A semiconductor structure is provided. The semiconductor structure includes a first fin and a second fin on a semiconductor substrate. The semiconductor structure also includes an epitaxial structure on the first fin and the second fin. The semiconductor structure further includes outer spacers on outer sidewalls of the epitaxial structure. In addition, the semiconductor structure includes an inner spacer structure between the first fin and the second fin and covering inner sidewalls of the epitaxial structure. A top surface of the inner spacer structure is exposed to an air gap formed between the epitaxial structure and the inner spacer structure.

公开(公告)号：US20240357804A1

公开(公告)日：2024-10-24

申请号：US18757580

申请日：2024-06-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： MENG-SHENG CHANG ,  CHIA-EN HUANG ,  YAO-JEN YANG ,  YIH WANG

IPC分类号： H10B20/20 ,  G06F12/14 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H10B99/00

CPC分类号： H10B20/20 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/42316 ,  H01L29/7851 ,  H10B99/00 ,  G06F12/1433

摘要： A memory device includes: a substrate; a semiconductor fin over the substrate in a first direction; a first gate electrode and a second gate electrode over the substrate in a second direction, the semiconductor fin extending through the second gate electrode and terminating at the first gate electrode; a first gate dielectric layer arranged between the semiconductor fin and the first gate electrode; and a second gate dielectric layer arranged between the semiconductor fin and the second gate electrode. The second gate electrode is configured as a read transistor of a first memory cell, in which the second gate dielectric layer is kept intact, and the first gate electrode is configured as a program transistor of the first memory cell, in which an occurrence or an absence of an electrical breakdown in the first gate dielectric layer represents a binary logic state of the first memory cell.