公开(公告)号：US20190333872A1

公开(公告)日：2019-10-31

申请号：US16227919

申请日：2018-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geun Won Lim ,  Seok Cheon Baek ,  Ji Sung Cheon ,  Jong Woo Shin ,  Bong Hyun Choi

IPC: H01L23/00 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.

公开(公告)号：US11791287B2

公开(公告)日：2023-10-17

申请号：US17462522

申请日：2021-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geun Won Lim ,  Seok Cheon Baek ,  Ji Sung Cheon ,  Jong Woo Shin ,  Bong Hyun Choi

IPC: H01L23/00 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/562 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.

公开(公告)号：US20210398915A1

公开(公告)日：2021-12-23

申请号：US17462522

申请日：2021-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geun Won Lim ,  Seok Cheon Baek ,  Ji Sung Cheon ,  Jong Woo Shin ,  Bong Hyun Choi

IPC: H01L23/00 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.

公开(公告)号：US11133267B2

公开(公告)日：2021-09-28

申请号：US16227919

申请日：2018-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geun Won Lim ,  Seok Cheon Baek ,  Ji Sung Cheon ,  Jong Woo Shin ,  Bong Hyun Choi

IPC: H01L27/11573 ,  H01L23/00 ,  H01L27/11582

Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.