公开(公告)号：US11626421B2

公开(公告)日：2023-04-11

申请号：US17196005

申请日：2021-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon Baek

IPC: H01L27/11582 ,  H01L21/02 ,  H01L21/768 ,  H01L29/10 ,  H01L23/48 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573

Abstract: A vertical memory device includes a substrate having a peripheral circuit interconnection, lower word lines stacked on the substrate, vertical channel structures passing through the lower word lines, a first cell contact plug including a bottom end lower than a bottom surface of a first lower word line and being connected to the first lower word line, and lower insulating layers and first lower mold patterns positioned beneath the first lower word line and stacked alternately on each other from the substrate.

公开(公告)号：US11056502B2

公开(公告)日：2021-07-06

申请号：US16365827

申请日：2019-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon Baek

IPC: H01L23/538 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L29/66 ,  H01L27/11568 ,  H01L27/11575

Abstract: A semiconductor device includes a substrate having a cell region and a connection region adjacent to the cell region. A lower stack structure and an upper stack structure are disposed on the substrate. A channel structure is provided to pass through the upper stack structure and the lower stack structure. A distance between a lower extension line portion included in an uppermost one of a plurality of lower interconnection layers and an upper extension line portion included in a lowermost one of a plurality of upper interconnection layers is less than a distance between a lower gate electrode portion included in the uppermost one of the plurality of lower interconnection layers and an upper gate electrode portion included in the lowermost one of the plurality of upper interconnection layers.

公开(公告)号：US10971432B2

公开(公告)日：2021-04-06

申请号：US16388370

申请日：2019-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok Cheon Baek

IPC: H01L23/48 ,  H01L27/11582 ,  H01L27/11556

Abstract: A semiconductor device includes a peripheral circuit area disposed on a first substrate and including circuit devices. A memory cell area is disposed on a second substrate and includes memory cells. A through wiring area includes a through contact plug and an insulating area. The through contact plug extends through the memory cell area and the second substrate and connects the memory cell area to the circuit devices. The insulating area surrounds the through contact plug. The insulating area includes a first insulating layer penetrating through the second substrate, a plurality of second insulating layers, a third insulating layer having a vertical extension portion, and a plurality of horizontal extension portions extended in parallel to a top surface of the second substrate from a side surface of the vertical extension portion to contact the second insulating layers.

公开(公告)号：US10930664B2

公开(公告)日：2021-02-23

申请号：US16454293

申请日：2019-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Hwan Son ,  Seok Cheon Baek ,  Ji Sung Cheon

IPC: H01L27/115 ,  H01L27/11578 ,  H01L27/11568 ,  H01L27/11565

Abstract: A semiconductor device may include a substrate and a stacked structure in which a plurality of insulating layers and a plurality of interconnection layers are alternately stacked on the substrate. An isolation region may cross the stacked structure in a first direction. A plurality of first structures may extend into the stacked structure in a second direction perpendicular to the first direction. A plurality of first patterns may extend into the stacked structure in the second direction in the isolation region. Bottoms of the plurality of first patterns may be farther from an upper surface of the substrate than bottoms of the plurality of channel structures.

公开(公告)号：US10535679B2

公开(公告)日：2020-01-14

申请号：US16136474

申请日：2018-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon Baek ,  Boh Chang Kim ,  Chung Ki Min ,  Ji Hoon Park ,  Byung Kwan You

IPC: H01L27/11582 ,  H01L29/423 ,  H01L23/00

Abstract: A semiconductor device includes lower gate electrodes placed on a substrate and spaced apart from one another; upper gate electrodes placed over the lower gate electrodes and spaced apart from one another; an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad; and a P-type pad extending from one end of at least one electrode to which the R-type pad is not connected among the lower gate electrodes or the upper gate electrodes and having a different thickness than the R-type pad, wherein the P-type pad includes a first pad connected to an uppermost lower gate electrode among the lower gate electrodes.

公开(公告)号：US10373975B2

公开(公告)日：2019-08-06

申请号：US16162720

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon Baek ,  Young Woo Kim ,  Dong Sik Lee ,  Min Yong Lee ,  Woong Seop Lee

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/06 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.

公开(公告)号：US10128263B2

公开(公告)日：2018-11-13

申请号：US15224238

申请日：2016-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon Baek ,  Young Woo Kim ,  Dong Sik Lee ,  Min Yong Lee ,  Woong Seop Lee

IPC: H01L29/76 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/06

Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.

公开(公告)号：US11791287B2

公开(公告)日：2023-10-17

申请号：US17462522

申请日：2021-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geun Won Lim ,  Seok Cheon Baek ,  Ji Sung Cheon ,  Jong Woo Shin ,  Bong Hyun Choi

IPC: H01L23/00 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/562 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.

公开(公告)号：US11145672B2

公开(公告)日：2021-10-12

申请号：US16706684

申请日：2019-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon Baek ,  Boh Chang Kim ,  Chung Ki Min ,  Ji Hoon Park ,  Byung Kwan You

IPC: H01L27/11582 ,  H01L23/00 ,  H01L29/423 ,  H01L27/11565 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/538 ,  H01L27/11531

Abstract: A semiconductor device includes lower gate electrodes placed on a substrate and spaced apart from one another; upper gate electrodes placed over the lower gate electrodes and spaced apart from one another; an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad; and a P-type pad extending from one end of at least one electrode to which the R-type pad is not connected among the lower gate electrodes or the upper gate electrodes and having a different thickness than the R-type pad, wherein the P-type pad includes a first pad connected to an uppermost lower gate electrode among the lower gate electrodes.

公开(公告)号：US10903229B2

公开(公告)日：2021-01-26

申请号：US16162533

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon Baek ,  Sung Hun Lee

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L29/423 ,  G11C7/18 ,  G11C8/14 ,  H01L27/1157 ,  G11C5/02

Abstract: A three-dimensional semiconductor memory device including a gate-stack structure on a base substrate, the gate-stack structure including gate electrodes stacked in a direction perpendicular to a surface of the base substrate and spaced apart from each other; a through region penetrating through the gate-stack structure and surrounded by the gate-stack structure; and first vertical channel structures and second vertical channel structures on both sides of the through region and penetrating through the gate-stack structure, wherein the through region is between the first vertical channel structures and the second vertical channel structures.