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公开(公告)号:US10930664B2
公开(公告)日:2021-02-23
申请号:US16454293
申请日:2019-06-27
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yoon Hwan Son , Seok Cheon Baek , Ji Sung Cheon
IPC: H01L27/115 , H01L27/11578 , H01L27/11568 , H01L27/11565
Abstract: A semiconductor device may include a substrate and a stacked structure in which a plurality of insulating layers and a plurality of interconnection layers are alternately stacked on the substrate. An isolation region may cross the stacked structure in a first direction. A plurality of first structures may extend into the stacked structure in a second direction perpendicular to the first direction. A plurality of first patterns may extend into the stacked structure in the second direction in the isolation region. Bottoms of the plurality of first patterns may be farther from an upper surface of the substrate than bottoms of the plurality of channel structures.
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公开(公告)号:US20200185402A1
公开(公告)日:2020-06-11
申请号:US16454293
申请日:2019-06-27
Applicant: Samsung Electronics Co., Ltd.
Inventor: YOON HWAN SON , Seok Cheon Baek , Ji Sung Cheon
IPC: H01L27/11578 , H01L27/11565 , H01L27/11568
Abstract: A semiconductor device may include a substrate and a stacked structure in which a plurality of insulating layers and a plurality of interconnection layers are alternately stacked on the substrate. An isolation region may cross the stacked structure in a first direction. A plurality of first structures may extend into the stacked structure in a second direction perpendicular to the first direction. A plurality of first patterns may extend into the stacked structure in the second direction in the isolation region. Bottoms of the plurality of first patterns may be farther from an upper surface of the substrate than bottoms of the plurality of channel structures.
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公开(公告)号:US20190333872A1
公开(公告)日:2019-10-31
申请号:US16227919
申请日:2018-12-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Geun Won Lim , Seok Cheon Baek , Ji Sung Cheon , Jong Woo Shin , Bong Hyun Choi
IPC: H01L23/00 , H01L27/11582 , H01L27/11573
Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.
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公开(公告)号:US11791287B2
公开(公告)日:2023-10-17
申请号:US17462522
申请日:2021-08-31
Applicant: Samsung Electronics Co., Ltd.
Inventor: Geun Won Lim , Seok Cheon Baek , Ji Sung Cheon , Jong Woo Shin , Bong Hyun Choi
CPC classification number: H01L23/562 , H10B43/27 , H10B43/40
Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.
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公开(公告)号:US11195856B2
公开(公告)日:2021-12-07
申请号:US16801278
申请日:2020-02-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Yoon Hwan Son , Ji Sung Cheon
IPC: H01L27/11582 , H01L27/11524 , H01L27/11573 , H01L27/11529 , H01L27/1157 , H01L27/11556
Abstract: A semiconductor device includes a first substrate in which a first region and a second region are defined, a first stack structure with first gate electrodes displaced and stacked sequentially on the first substrate, a second stack structure with second gate electrodes displaced and stacked sequentially on the first stack structure, a junction layer disposed between the first stack structure and the second stack structure, a first interlayer insulating layer disposed on a side surface of the first stack structure, a second interlayer insulating layer covering the second stack structure, a first channel hole that penetrates through structure(s) and/or layer(s) and a second channel hole that penetrates through structure(s) and/or layer(s). A height of the second portion of the first channel hole in a second direction orthogonal to the first direction is less than a height of the second portion of the second channel hole in the second direction.
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公开(公告)号:US11903206B2
公开(公告)日:2024-02-13
申请号:US17747174
申请日:2022-05-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jong Seon Ahn , Ji Sung Cheon , Young Jin Kwon , Seok Cheon Baek , Woong Seop Lee
CPC classification number: H10B43/27 , H01L29/40117 , H01L29/4234 , H10B43/10 , H10B43/35 , H10B43/40
Abstract: A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.
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公开(公告)号:US11342351B2
公开(公告)日:2022-05-24
申请号:US16257357
申请日:2019-01-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jong Seon Ahn , Ji Sung Cheon , Young Jin Kwon , Seok Cheon Baek , Woong Seop Lee
IPC: H01L23/528 , H01L27/11 , H01L27/11582 , H01L27/1157 , H01L29/423 , H01L27/11573 , H01L27/11565 , H01L21/28
Abstract: A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.
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公开(公告)号:US20210398915A1
公开(公告)日:2021-12-23
申请号:US17462522
申请日:2021-08-31
Applicant: Samsung Electronics Co., Ltd.
Inventor: Geun Won Lim , Seok Cheon Baek , Ji Sung Cheon , Jong Woo Shin , Bong Hyun Choi
IPC: H01L23/00 , H01L27/11573 , H01L27/11582
Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.
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公开(公告)号:US11133267B2
公开(公告)日:2021-09-28
申请号:US16227919
申请日:2018-12-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Geun Won Lim , Seok Cheon Baek , Ji Sung Cheon , Jong Woo Shin , Bong Hyun Choi
IPC: H01L27/11573 , H01L23/00 , H01L27/11582
Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.
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