公开(公告)号：US20220102370A1

公开(公告)日：2022-03-31

申请号：US17324411

申请日：2021-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghoon KWON ,  Junsuk KIM ,  Jongheun LIM

IPC: H01L27/11575 ,  H01L23/535 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/768

Abstract: A memory device includes a cell stacked structure on a substrate, the cell stacked structure including insulation layers and gate patterns alternately stacked, a channel structure passing through the cell stacked structure, the channel structure extending in a vertical direction, a dummy structure on the substrate, the dummy structure being spaced apart from the cell stacked structure, and the dummy structure including insulation layers and metal patterns alternately stacked, a first through via contact passing through the dummy structure, the first through via contact extending in the vertical direction, and a first capping insulation pattern between a sidewall of the first through via contact and each of the metal patterns in the dummy structure, the first capping insulation pattern insulating the first through via contact from each of the metal patterns.

公开(公告)号：US20210375905A1

公开(公告)日：2021-12-02

申请号：US17140277

申请日：2021-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changsun HWANG ,  Youngjin KWON ,  Gihwan KIM ,  Hansol SEOK ,  Dongseog EUN ,  Jongheun LIM

IPC: H01L27/11573 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

Abstract: An integrated circuit device includes: a substrate having a cell region, a peripheral circuit region, and an interconnection region between the cell region and the peripheral circuit region; a first cell stack structure and a second cell stack structure on the first cell stack structure, each including a plurality of insulating layers and a plurality of word line structures alternately stacked on the substrate; and a dummy stack structure located at a same vertical level as the second cell stack structure, and including a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked in the peripheral circuit region.

公开(公告)号：US20210159242A1

公开(公告)日：2021-05-27

申请号：US16903514

申请日：2020-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok JANG ,  Chang-Sun HWANG ,  Chungki MIN ,  Kieun SEO ,  Jongheun LIM

IPC: H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/535 ,  H01L21/768

Abstract: A three-dimensional semiconductor memory device including a peripheral circuit structure on a first substrate, the peripheral circuit structure including peripheral circuits, a second substrate on the peripheral circuit structure, an electrode structure on the second substrate, the electrode structure including a plurality of electrodes that are stacked on the second substrate and a penetrating interconnection structure penetrating the electrode structure and the second substrate may be provided. The penetrating interconnection structure may include a lower insulating pattern, a mold pattern structure on the lower insulating pattern, a protection pattern between the lower insulating pattern and the mold pattern structure, and a penetration plug. The penetration plug may penetrate the mold pattern structure and the lower insulating pattern and may be connected to the peripheral circuit structure. The protection pattern may be at a level lower than that of the lowermost one of the electrodes.