公开(公告)号：US20220254802A1

公开(公告)日：2022-08-11

申请号：US17473141

申请日：2021-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon KWON ,  Chang-Sun HWANG ,  Chungki MIN

IPC: H01L27/11575 ,  H01L23/535 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device includes an upper-level layer having a cell array region, a cell contact region and a dummy region on a substrate. The upper-level layer includes a semiconductor layer, a cell array structure including first and second stack structures sequentially stacked on the semiconductor layer of the cell array region, the first and second stack structures comprising stacked electrodes, a first staircase structure on the semiconductor layer of the cell contact region, the electrodes extending from the cell array structure into the first staircase structure such that the cell array structure is connected to the first staircase structure, a vertical channel structure penetrating the cell array structure, a dummy structure in the dummy region, the dummy structure at the same level as the second stack structure, the dummy structure including stacked first layers, and cell contact plugs in the cell contact region and connected to the first staircase structure.

公开(公告)号：US20190091828A1

公开(公告)日：2019-03-28

申请号：US15926244

申请日：2018-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suk-Hoon JEONG ,  Sang-Hak LEE ,  Geun-Kyu CHOI ,  Chang-Sun HWANG ,  Tae-Young KWON ,  Young-Sang KIM ,  Hyung-Kyu JIN ,  Jeong-Nam HAN

IPC: B24B37/015 ,  B24B37/26 ,  B24B49/14 ,  B24B55/02

CPC classification number: B24B37/015 ,  B24B37/26 ,  B24B49/14 ,  B24B55/02

Abstract: A method of controlling a chemical mechanical polishing (CMP) process, a temperature control, and a CMP apparatus, the method including measuring actual temperatures of at least two regions in a platen in real time during the CMP process in which a polishing pad attached to the platen polishes a substrate held by a polishing head using slurry and deionized water; receiving the measured actual temperatures of the regions; and individually controlling the actual temperatures of the regions in real time during the CMP process to provide the regions with a predetermined set CMP process temperature.

公开(公告)号：US20210159242A1

公开(公告)日：2021-05-27

申请号：US16903514

申请日：2020-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok JANG ,  Chang-Sun HWANG ,  Chungki MIN ,  Kieun SEO ,  Jongheun LIM

IPC: H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/535 ,  H01L21/768

Abstract: A three-dimensional semiconductor memory device including a peripheral circuit structure on a first substrate, the peripheral circuit structure including peripheral circuits, a second substrate on the peripheral circuit structure, an electrode structure on the second substrate, the electrode structure including a plurality of electrodes that are stacked on the second substrate and a penetrating interconnection structure penetrating the electrode structure and the second substrate may be provided. The penetrating interconnection structure may include a lower insulating pattern, a mold pattern structure on the lower insulating pattern, a protection pattern between the lower insulating pattern and the mold pattern structure, and a penetration plug. The penetration plug may penetrate the mold pattern structure and the lower insulating pattern and may be connected to the peripheral circuit structure. The protection pattern may be at a level lower than that of the lowermost one of the electrodes.