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    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200185398A1

    公开(公告)日：2020-06-11

    申请号：US16793301

    申请日：2020-02-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Miso SHIN ,  Myeongan KWON ,  Chungki MIN ,  Byoungho KWON ,  Boun YOON

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11548 ,  H01L27/11529 ,  H01L27/11519

    Abstract: Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate including a peripheral circuit region and a cell array region, peripheral gate stacks provided on the peripheral circuit region of the substrate, and an electrode structure provided on the cell array region of the substrate. The electrode structure may include a lower electrode, a lower insulating layer covering the lower electrode, and upper electrodes and upper insulating layers, which are vertically and alternately stacked on the lower insulating layer. The lower insulating layer may be extended from the cell array region to the peripheral circuit region to cover the peripheral gate stacks, and a top surface of the lower insulating layer may be higher on the peripheral circuit region than on the cell array region.

    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20220384477A1

    公开(公告)日：2022-12-01

    申请号：US17574740

    申请日：2022-01-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Donghoon KWON ,  Chungki MIN

    IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

    Abstract: A semiconductor device includes a peripheral circuit structure including a lower substrate, a plurality of circuits formed on the lower substrate, and a plurality of wiring layers connected to the plurality of circuits, an upper substrate covering the peripheral circuit structure and including a through opening, a memory stack structure including a plurality of gate lines, a memory cell contact passing through at least one of the plurality of gate lines to contact one gate line from among the plurality of gate lines, the memory cell contact extending to the peripheral circuit structure through the through opening and being configured to be electrically connected to a first wiring layer from among the plurality of wiring layers, and a plurality of dummy channel structures passing through at least one of the plurality of gate lines to extend to the peripheral circuit structure through the through opening.

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 审中-公开
    半导体器件及其形成方法

    公开(公告)号：US20140220754A1

    公开(公告)日：2014-08-07

    申请号：US14064516

    申请日：2013-10-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chungki MIN

    IPC: H01L29/66

    CPC classification number: H01L29/66833 ,  H01L21/7682 ,  H01L21/76834 ,  H01L27/11568

    Abstract: A method of forming a semiconductor device includes forming first sacrificial patterns on a substrate, the first sacrificial patterns spaced apart from each other, forming a capping layer on the first sacrificial patterns, forming a gap insulating layer spaced apart from a lower portion of the capping layer between the first sacrificial patterns in a vertical direction, planarizing the gap insulating layer and the capping layer to expose the first sacrificial patterns, removing the first sacrificial patterns to form trenches, and forming conductive patterns in the trenches, the conductive patterns having an air gap therebetween and between the lower portion of the capping layer and the gap insulating layer.

    Abstract translation: 形成半导体器件的方法包括在衬底上形成第一牺牲图案，第一牺牲图案彼此间隔开，在第一牺牲图案上形成覆盖层，形成与封盖的下部分隔开的间隙绝缘层 在垂直方向上在第一牺牲图案之间，平坦化间隙绝缘层和覆盖层以暴露第一牺牲图案，去除第一牺牲图案以形成沟槽，以及在沟槽中形成导电图案，导电图案具有空气 并且在封盖层的下部和间隙绝缘层之间。

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