公开(公告)号：US20200152535A1

公开(公告)日：2020-05-14

申请号：US16672652

申请日：2019-11-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghawn BAE ,  Doohwan LEE ,  Jooyoung CHOI

IPC: H01L23/31 ,  H01L21/48 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00

Abstract: The invention provides a semiconductor package, which may include a connection structure including one or more redistribution layers. A semiconductor chip is disposed on the connection structure and has an active surface on which a connection pad electrically connected to the redistribution layer is disposed and an inactive surface opposite to the active surface. An encapsulant is disposed on the connection structure and covers at least a portion of the inactive surface of the semiconductor chip. A conductor pattern layer is embedded in the encapsulant such that one exposed surface of the conductor pattern layer is exposed from the encapsulant. A metal layer is disposed on the encapsulant and covers the one exposed surface of the conductor pattern layer.

公开(公告)号：US20250105117A1

公开(公告)日：2025-03-27

申请号：US18619711

申请日：2024-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangseok HONG ,  Jaeseong KIM ,  Jeongseok KIM ,  Tae Wook KIM ,  Yejin LEE ,  Jooyoung CHOI

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package may include a semiconductor chip, a redistribution layer on the semiconductor chip, a protection pattern covering the redistribution layer, and a connection terminal on the redistribution layer. The redistribution layer may include a redistribution pad on a top surface of the redistribution layer, and the redistribution pad may include a first pad and a second pad on the first pad. The second pad may have a side surface that is inclined and that extends to a top surface of the first pad, and the protection pattern may be spaced apart from the side surface of the second pad and may have a side surface that is inclined and that extends to the top surface of the first pad.

公开(公告)号：US20250079319A1

公开(公告)日：2025-03-06

申请号：US18737402

申请日：2024-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongseok KIM ,  Jaeseong KIM ,  Tae Wook KIM ,  Yejin LEE ,  Jooyoung CHOI ,  Sangseok HONG

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L23/49 ,  H01L23/498 ,  H01L25/16 ,  H01Q1/22

Abstract: A semiconductor package may include a first redistribution substrate, a first semiconductor chip disposed on the first redistribution substrate, a second semiconductor chip horizontally spaced apart from the first semiconductor chip, a mold layer provided on the first redistribution substrate to enclose the first and second semiconductor chips, a second redistribution substrate disposed on the mold layer, a connection member, which is provided at a side of the first and second semiconductor chips to connect the first redistribution substrate to the second redistribution substrate, and an antenna substrate attached to the second redistribution substrate using an adhesive layer. The antenna substrate may include a core portion, an antenna pattern provided on a top surface of the core portion, and a wiring pattern provided on a bottom surface of the core portion.

公开(公告)号：US20220278011A1

公开(公告)日：2022-09-01

申请号：US17749825

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghawn BAE ,  Doohwan LEE ,  Jooyoung CHOI

IPC: H01L23/31 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/373 ,  H01L23/367

Abstract: Provided is method of manufacturing a semiconductor device. The method includes: forming a metal layer on a carrier; forming a conductor pattern layer on the metal layer; mounting a semiconductor chip on a tape; forming an encapsulant covering the semiconductor chip; attaching the conductor pattern layer to the encapsulant; removing the tape; and forming a connection structure electrically connected to the semiconductor chip in an area from which the tape is removed.

公开(公告)号：US20250105192A1

公开(公告)日：2025-03-27

申请号：US18635296

申请日：2024-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Wook KIM ,  Jaeseong KIM ,  Jeongseok KIM ,  Yejin LEE ,  Jooyoung CHOI ,  Sangseok HONG

IPC: H01L23/00 ,  H01L21/762 ,  H01L23/498 ,  H01L23/522 ,  H01L25/00 ,  H01L25/18

Abstract: A semiconductor package may include a redistribution layer structure including a redistribution layer, a semiconductor chip a first surface of the redistribution layer structure, an under-bump structure disposed on a second surface of the redistribution layer structure and including a protective layer having a trench and an under-bump metal layer, an electronic element on the under-bump structure, and an underfill member filling at least a portion of a space between the under-bump structure and the electronic element and filling at least a portion of the trench, wherein, in a plan view, the trench surrounds the electronic element and may include a protrusion portion protruding outward from the electronic element in a region surrounding an edge of the electronic element.

公开(公告)号：US20250046769A1

公开(公告)日：2025-02-06

申请号：US18665893

申请日：2024-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooyoung CHOI ,  Dahee KIM ,  Jeongseok KIM ,  Gyujin CHOI ,  Jaehoon CHOI

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16

Abstract: A semiconductor package may include a package redistribution layer including a plurality of package redistribution patterns and a package redistribution insulating layer surrounding the plurality of package redistribution patterns, a plurality of electronic components apart from each other in a horizontal direction on the package redistribution layer and including at least one sub package, a package molding layer covering a top surface of the package redistribution layer and surrounding the plurality of electronic components, and a plurality of package connection terminals attached to a bottom surface of the package redistribution layer in a fan-out manner. The at least one sub package may include a package substrate, a semiconductor chip attached to the package substrate, and a sub molding layer on the package substrate.

公开(公告)号：US20250149518A1

公开(公告)日：2025-05-08

申请号：US18744994

申请日：2024-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yejin LEE ,  Dahee KIM ,  Jaeseong KIM ,  Jeongseok KIM ,  Taewook KIM ,  Gyujin CHOI ,  Jooyoung CHOI ,  Sangseok HONG

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498

Abstract: Provided is a semiconductor package including a first redistribution layer, a semiconductor device on the first redistribution layer, a substrate protection layer below the first redistribution layer, a groove in a bottom surface of the substrate protection layer, a passive device in the groove, an underfill between the passive device and the groove, and a dam apart from the passive device, the dam protruding from the substrate protection layer and at least partially surrounding the passive device.