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    SEMICONDUCTOR PACKAGE
    1.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220328415A1

    公开(公告)日：2022-10-13

    申请号：US17849938

    申请日：2022-06-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Changeun JOO ,  Gyujin CHOI

    IPC: H01L23/538 ,  H01L23/498

    Abstract: A semiconductor package includes a core substrate having a through hole, a first molding member at least partially filling the through hole and covering an upper surface of the core substrate, the first molding member having a cavity within the through hole, a first semiconductor chip on the first molding member on the upper surface of the core substrate, a second semiconductor chip arranged within the cavity, a second molding member on the first molding member and covering the first semiconductor chip, a third molding member filling the cavity and covering the lower surface of the core substrate; first redistribution wirings on the second molding member and electrically connecting first chip pads of the first semiconductor chip and core connection wirings of the core substrate; and second redistribution wirings on the third molding member and electrically connecting second chip pads of the second semiconductor chip and the core connection wirings.

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
    2.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210265274A1

    公开(公告)日：2021-08-26

    申请号：US17032210

    申请日：2020-09-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Changeun JOO ,  Gyujin CHOI

    IPC: H01L23/538 ,  H01L23/498

    Abstract: A semiconductor package includes a core substrate having a through hole, a first molding member at least partially filling the through hole and covering an upper surface of the core substrate, the first molding member having a cavity within the through hole, a first semiconductor chip on the first molding member on the upper surface of the core substrate, a second semiconductor chip arranged within the cavity, a second molding member on the first molding member and covering the first semiconductor chip, a third molding member filling the cavity and covering the lower surface of the core substrate; first redistribution wirings on the second molding member and electrically connecting first chip pads of the first semiconductor chip and core connection wirings of the core substrate; and second redistribution wirings on the third molding member and electrically connecting second chip pads of the second semiconductor chip and the core connection wirings.

    SEMICONDUCTOR PACKAGE INCLUDING A REDISTRIBUTION STRUCTURE
    4.
    发明申请
    SEMICONDUCTOR PACKAGE INCLUDING A REDISTRIBUTION STRUCTURE 有权

    公开(公告)号：US20250079317A1

    公开(公告)日：2025-03-06

    申请号：US18813120

    申请日：2024-08-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Changyeon SONG ,  Dongwon KANG ,  Sunguk LEE ,  Jaeean LEE ,  Gyujin CHOI

    IPC: H01L23/532 ,  H01L23/14 ,  H01L23/522 ,  H01L23/528

    Abstract: A semiconductor package according to an embodiment includes a first substrate having an upper surface and a lower surface and a cavity extending from the upper surface to the lower surface; a first chip mounted in the cavity; a first redistribution structure disposed on the first chip; a passive element mounted inside the first redistribution structure; and an adhesive layer disposed below the passive element. The first redistribution structure includes a plurality of redistribution insulating layers stacked in a vertical direction on the first chip, and a first redistribution pattern and a second redistribution pattern located within the redistribution insulating layers. The first redistribution pattern is disposed below a recess vertically penetrating at least one redistribution insulating layer among the plurality of redistribution insulating layers. The second redistribution pattern is adjacent to the recess in a lateral direction.

    SEMICONDUCTOR PACKAGE
    5.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250096201A1

    公开(公告)日：2025-03-20

    申请号：US18599390

    申请日：2024-03-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Gyujin CHOI ,  Dahee KIM ,  Hwan Pil PARK ,  Taehoon LEE ,  Younjeong CHOE

    IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16

    Abstract: The present disclosure relates to a semiconductor package which includes a wiring structure including insulating layers, wiring layers, and vias, a chip stack structure including a plurality of semiconductor chips and being oblique on the wiring structure such that the plurality of semiconductor chips are inclined with respect to the wiring structure, and a sealing material encapsulating the chip stack structure, wherein each of the plurality of semiconductor chips includes connection pads on one surface of the semiconductor chip, and the plurality of semiconductor chips are being offset with each other such that the connection pads are exposed, and each of the connection pads of each of the plurality of semiconductor chips is in contact with one of the vias and connected to the wiring layers.

    METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
    7.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210183677A1

    公开(公告)日：2021-06-17

    申请号：US17007433

    申请日：2020-08-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Gyujin CHOI ,  Changeun JOO

    IPC: H01L21/68 ,  H01L21/66 ,  H01L21/56 ,  H01L23/00 ,  H01L21/768 ,  H01L21/48

    Abstract: In a method of manufacturing a semiconductor package, a plurality of semiconductor chips are encapsulated in a carrier to provide encapsulated semiconductor chips. A first surface of the encapsulated semiconductor chips includes chip pads exposed from a first surface of the carrier. An alignment error of each of the semiconductor chips with respect to the carrier is measured. A redistribution wiring structure may be formed on the first surface of the carrier. Correction values for each layer of the redistribution wiring structure may be reflected while forming the redistribution wiring structure in order to correct the alignment error while forming the redistribution wiring structure. The redistribution wiring structure may have redistribution wirings electrically connected to the chip pads on the first surface of the carrier. Outer connection members may be formed on the redistribution wiring structure and may be configured to be electrically connected to the outermost redistribution wirings.

    SEMICONDUCTOR PACKAGE
    8.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250046769A1

    公开(公告)日：2025-02-06

    申请号：US18665893

    申请日：2024-05-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jooyoung CHOI ,  Dahee KIM ,  Jeongseok KIM ,  Gyujin CHOI ,  Jaehoon CHOI

    IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16

    Abstract: A semiconductor package may include a package redistribution layer including a plurality of package redistribution patterns and a package redistribution insulating layer surrounding the plurality of package redistribution patterns, a plurality of electronic components apart from each other in a horizontal direction on the package redistribution layer and including at least one sub package, a package molding layer covering a top surface of the package redistribution layer and surrounding the plurality of electronic components, and a plurality of package connection terminals attached to a bottom surface of the package redistribution layer in a fan-out manner. The at least one sub package may include a package substrate, a semiconductor chip attached to the package substrate, and a sub molding layer on the package substrate.

    SEMICONDUCTOR PACKAGE INCLUDING UNDER BUMP METALLIZATION PAD
    9.
    发明申请
    SEMICONDUCTOR PACKAGE INCLUDING UNDER BUMP METALLIZATION PAD 有权

    公开(公告)号：US20220165693A1

    公开(公告)日：2022-05-26

    申请号：US17343992

    申请日：2021-06-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaeean LEE ,  Changeun JOO ,  Gyujin CHOI

    IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

    Abstract: A semiconductor package including a semiconductor chip; a lower redistribution layer on a lower surface of the semiconductor chip; a lower passivation layer on a lower surface of the lower redistribution layer; a UBM pad on the lower passivation layer and including an upper pad and a lower pad connected to the upper pad, the upper pad having a greater horizontal length at an upper surface thereof than a horizontal length at a lower surface thereof; a seed layer between the lower passivation layer and the UBM pad; and an external connecting terminal on a lower surface of the UBM pad, wherein the seed layer includes a first seed part covering a side surface of the upper pad, a second seed part covering a portion of the lower surface of the upper pad, and a third seed part covering a portion of a side surface of the lower pad.

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