公开(公告)号：US20230140230A1

公开(公告)日：2023-05-04

申请号：US18146732

申请日：2022-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyongho KIM ,  Changsik Yoo ,  Kyungmin Kim

IPC: H04L1/00

Abstract: Disclosed is a transmitter which includes an encoder and a transmission interface circuit. The encoder receives data bits and generates conversion bits, a number of is the conversion bits being more than a number of the data bits, based on the number of the data bits. The encoder detects a risk pattern of the conversion bits to generate detection data and converts the risk pattern into a replacement pattern based on the detection data to generate code bits, a number of is the code bits being equal to the number of the conversion bits.

公开(公告)号：US20230143912A1

公开(公告)日：2023-05-11

申请号：US17985599

申请日：2022-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungho RYU ,  Kyongho KIM ,  Yongyun PARK ,  Kilhoon LEE ,  Yeongcheol RHEE ,  Taeho LEE ,  Hyunwook LIM

IPC: G09G5/00

CPC classification number: G09G5/008 ,  G09G2370/04

Abstract: Provided is a display driving circuit. The display driving circuit includes a clock data recovery circuit configured to receive a data signal and generate a clock signal and a first output data signal, an eye margin test circuit configured to sample the data signal by using the clock signal, based on a vertical measurement voltage and generate a second output data signal, and a bit error check circuit configured to measure a bit error rate of the data signal, based on the first output data signal and the second output data signal, wherein the clock data recovery circuit includes a jitter generator configured to generate jitter of the clock signal such that a jitter amplitude varies according to a horizontal control signal.

公开(公告)号：US20210328713A1

公开(公告)日：2021-10-21

申请号：US17144425

申请日：2021-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyongho KIM ,  Changsik YOO ,  Kyungmin KIM

IPC: H04L1/00

Abstract: Disclosed is a transmitter which includes an encoder and a transmission interface circuit. The encoder receives data bits and generates conversion bits, a number of is the conversion bits being more than a number of the data bits, based on the number of the data bits. The encoder detects a risk pattern of the conversion bits to generate detection data and converts the risk pattern into a replacement pattern based on the detection data to generate code bits, a number of is the code bits being equal to the number of the conversion bits.

公开(公告)号：US20170116954A1

公开(公告)日：2017-04-27

申请号：US15271837

申请日：2016-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hoon BAEK ,  Hyunwook LIM ,  Kwi Sung YOO ,  Eun-Young JIN ,  Kyongho KIM ,  JaeYoul LEE ,  Youngmin CHOI

IPC: G09G5/00 ,  H03L7/089 ,  H03L7/093 ,  H03L7/08 ,  H03L7/099

CPC classification number: G09G5/008 ,  G09G3/2096 ,  G09G2310/027 ,  G09G2330/10 ,  G09G2370/10 ,  G09G2370/16 ,  H03L7/0807 ,  H03L7/0891 ,  H03L7/095

Abstract: A clock and data recovery circuit in accordance with an embodiment of the inventive concept includes a phase locked loop configured to receive a data stream into which an additional bit is inserted at every reference period to generate parallelized data and a clock signal, and a first detector circuit configured to determine whether the parallelized data is locked based on a bit-conversion of the data stream according to an insertion of the additional bit. The bit-conversion is executed with respect to the additional bits according to a predetermined protocol, or is executed with respect to at least one bit from among data of the data stream between a current one of the additional bits and a next one of the additional bits.