公开(公告)号：US20230185452A1

公开(公告)日：2023-06-15

申请号：US17865621

申请日：2022-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngsuk RA ,  Hanbyeul NA ,  Kwanwoo NOH ,  Mankeun SEO ,  Hong Rak SON ,  Jae Hun JANG

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0655 ,  G06F3/0679

Abstract: A method of operating a storage controller includes receiving raw data indicating a series of bits each corresponding to one of threshold voltage states, performing a first state shaping for reducing a number of first target bits of the series of bits, logical values of the first target bits being equal to a logical value of a target threshold voltage state of the threshold voltage states in a first page of plural pages, generating first indicator data that indicates the first target bits based on the first state shaping, compressing the first indicator data, and storing the compressed first indicator data.

公开(公告)号：US20250021431A1

公开(公告)日：2025-01-16

申请号：US18635073

申请日：2024-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junho SHIN ,  Hanbyeul NA ,  Jaehun JANG ,  Mankeun SEO ,  Dongmin SHIN

IPC: G06F11/10

Abstract: A memory controller including: a data formatter receiving first to N-th hard decision data and first to N-th soft decision data, and performing a formatting operation on the first to N-th hard decision data and the first to N-th soft decision data; and an error correction code (ECC) circuit receiving the first to N-th hard decision data and the first to N-th soft decision data from the data formatter and correcting an error on the first page by ECC decoding processing, wherein the data formatter performs the formatting operation such that the first to N-th hard decision data and the first to N-th soft decision data are provided to the ECC circuit in an order different from an order of the first to N-th hard decision data and the first to N-th soft decision data were received from the memory device.

公开(公告)号：US20240289267A1

公开(公告)日：2024-08-29

申请号：US18384646

申请日：2023-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohyeon KIM ,  Hong Rak SON ,  Jae Hun JANG ,  Mankeun SEO ,  Yong Ho SONG

IPC: G06F12/02

CPC classification number: G06F12/023

Abstract: The present disclosure provides method and apparatuses for managing memory of storage system. In some embodiments, a controller of a storage system includes a memory storing a program, and a processor configured to execute the program to determine whether a type of data stored in the memory is at least one of a first data type and a second data type, store, in the memory, a header of the data stored in the memory, based on a first determination that the data stored in the memory is of the first data type, compress the data stored in the memory, based on a second determination that data stored in the memory is of the second data type, and power off the memory based on at least one of the header of the data and the compressed data having been stored in the memory.

公开(公告)号：US20250103288A1

公开(公告)日：2025-03-27

申请号：US18818742

申请日：2024-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hun JANG ,  Hong Rak SON ,  Dong-Min SHIN ,  JongYoon YOON ,  Younho JEON ,  Sejung KWON ,  Byeoungwook KIM ,  Baeseong PARK ,  Mankeun SEO ,  Byungmin AHN ,  Dongsoo LEE

IPC: G06F7/485 ,  G06F5/01 ,  G06F7/22

Abstract: Disclosed is an accelerator performing an accumulation operation on a plurality of data, each being a floating point type. A method of operating the accelerator includes loading first data, finding a first exponent, which is a maximum value among exponents of the first data, generating aligned first fractions by performing a bit shift on first fractions of the first data based on the first exponent, and generating a first accumulated value by an accumulation operation on the aligned first fractions, loading second data, finding a second exponent, which is a maximum value among exponents of the second data, and generating a first aligned accumulated value by a bit shift on the first accumulated value, generating aligned second fractions by a bit shift on second fractions of the second data, and generating a second accumulated value by an accumulation operation on the aligned second fractions and the first aligned accumulated value.