DYNAMIC RESERVE CAPACITY IN STORAGE SYSTEMS
    1.
    发明公开

    公开(公告)号:US20240354015A1

    公开(公告)日:2024-10-24

    申请号:US18138415

    申请日:2023-04-24

    CPC classification number: G06F3/064 G06F3/0608 G06F3/067

    Abstract: Techniques are provided for managing a dynamic reserve capacity of a block storage system. A storage control system partitions a storage capacity of at least one storage device into a plurality of blocks for storing data. A data access operation is performed by the storage control system which results in invalidating at least a portion of data stored in a given block. In response to the invalidating, the storage control system determines a degree of invalid data in the given block, and compares the determined degree of invalid data to a utilization threshold. The storage control system designates the given block as fully utilized in response to determining that the degree of invalid data does not exceed the utilization threshold, and designates a capacity of the given block that is occupied by the invalid data to be part of a reserve capacity of the at least one storage device.

    Automatic deletion in a persistent storage device

    公开(公告)号:US12124727B2

    公开(公告)日:2024-10-22

    申请号:US17583022

    申请日:2022-01-24

    CPC classification number: G06F3/0652 G06F3/0608 G06F3/0679

    Abstract: A system and method for automatic deletion in a persistent storage device. In some embodiments, the method includes: receiving, by a persistent storage device, a first read command, for a first logical block of data; determining that a total number of read operations, for the first logical block of data, equals or exceeds a first threshold value; and in response to determining that the total number of read operations, for the first logical block of data, equals or exceeds the first threshold value, arranging for deletion of the first logical block of data from the persistent storage device.

    Processing device for handling misaligned data

    公开(公告)号:US12124699B2

    公开(公告)日:2024-10-22

    申请号:US18053948

    申请日:2022-11-09

    Abstract: A new type of instruction and a control register for the new type of instruction are provided to handle data that may be misaligned in memory. A first part of data (which may be misaligned in memory) is loaded into a first set of registers by loading a first atom containing the first part of data into registers. The pack instruction is executed by an execution unit to place part of data (whose length and starting position are indicated by second and third values in a control register) from one set of registers into an identified location (identified by a first value in the control register) in another set of registers.

    MANAGING DATA STORAGE CONSOLIDATION
    5.
    发明公开

    公开(公告)号:US20240345751A1

    公开(公告)日:2024-10-17

    申请号:US18299354

    申请日:2023-04-12

    Abstract: A technique consolidates data at multiple levels of granularity, the levels including a first level based on whole PLBs (physical large blocks) and a second level based on portions of donor PLBs. The technique further includes tracking PLBs in multiple PLB queues arranged based on storage utilization of the PLBs, and tracking PLB portions in multiple portion queues arranged based on storage utilization of the portions. When consolidating data to create a new PLB, a set of whole PLBs is selected, based on utilization, from the PLB queues, and a set of portions of donor PLBs is selected, based on utilization, from the portion queues. The selections are performed such that the total data size of the selected whole PLB(s) and the selected portion(s) fit within the new PLB.

    DETECTION AND LATENCY REDUCTION OF WRITE-INTENSIVE PROCEDURES IN A MEMORY SYSTEM

    公开(公告)号:US20240345732A1

    公开(公告)日:2024-10-17

    申请号:US18625007

    申请日:2024-04-02

    CPC classification number: G06F3/0611 G06F3/0608 G06F3/0659 G06F3/0679

    Abstract: Methods, systems, and devices for detection and latency reduction of write-intensive procedures in a memory system are described. A memory system may determine that a set of write commands share a group identifier associated with a writeback procedure or target a swap area of the non-volatile memory associated with a swap procedure. The memory system may determine that the writeback procedure or the swap procedure has been. The memory system may write, based on determining that the writeback procedure or the swap procedure has been initiated, data associated with the set of write commands to the non-volatile memory using a first type of write operation that has lower latency than a second type of write operation.

    Encoder and decoder
    8.
    发明授权

    公开(公告)号:US12119843B2

    公开(公告)日:2024-10-15

    申请号:US18178437

    申请日:2023-03-03

    Inventor: Takashi Takemoto

    CPC classification number: H03M7/30 G06F3/0608 G06F3/064 G06F3/0679

    Abstract: An entropy code encoder includes a register and first, second, third, and fourth arithmetic circuits. The first arithmetic circuit is configured to output, based on an input symbol, a first value corresponding to an appearance frequency of the input symbol and a second value corresponding to a cumulative distribution of the first value. The second arithmetic circuit is configured to output a third value corresponding to division of a value of bits in the register by the first value. The third arithmetic circuit is configured to output a fourth value obtained by adding the second value to a bit-shifted value of the third value, to update a value in the register. The fourth arithmetic circuit is configured to compare the value of upper bits in the register and the first value and output a value of lower bits in the register as a compressed data stream.

    Systems and methods for centralized logging for enhanced scalability and security of web services

    公开(公告)号:US12099473B1

    公开(公告)日:2024-09-24

    申请号:US17120623

    申请日:2020-12-14

    Abstract: A logging management server is provided for enhanced centralized monitoring of cloud computing platforms. The processor is configured to receive logging data sub-streams from the cloud computing platform. Each of the logging data sub-streams includes compressed logging data. The processor is also configured to apply a transformation function to each of the logging data sub-streams to obtain a transformed centralized logging data stream. The processor is further configured to transmit the transformed centralized logging data stream to write to a centralized object storage container. The processor is also configured to decompress a portion of the compressed logging data of the centralized logging data stream. The processor is further configured to identify the appended account identifier and the appended log group associated with the decompressed portion of logging data. The processor is also configured to route the decompressed portion of logging data to a sorted object storage container.

    RUNTIME STORAGE CAPACITY REDUCTION AVOIDANCE IN SEQUENTIALLY-WRITTEN MEMORY DEVICES

    公开(公告)号:US20240311004A1

    公开(公告)日:2024-09-19

    申请号:US18675934

    申请日:2024-05-28

    Abstract: A system includes a memory device having a plurality of blocks. A first subset of the plurality of blocks is configured as single-level cell (SLC) memory and a second subset of the plurality of blocks is configured as multi-level cell (MLC) memory. A processing device, operatively coupled to the memory device, determines that a first block of a set of blocks of the first subset is a bad block, wherein the first block is located in a first plane of the memory device. The processing device converts a second block of the set of blocks to the MLC memory of the second subset, wherein the second block is located in a second plane of the memory device, and wherein the second plane is neighboring the first plane.

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