公开(公告)号：US20170077103A1

公开(公告)日：2017-03-16

申请号：US15202874

申请日：2016-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-sung Park ,  ln-seak Hwang ,  Bo-un Yoon ,  Byoung-ho Kwon ,  Jong-hyuk Park ,  Jae-hee Kim ,  Myung-jae Jang

IPC: H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/90

Abstract: A method of manufacturing a semiconductor device includes: preparing a wafer in which a first cell area and a second cell area are defined; forming a bottom electrode structure in the first cell area and a dummy structure located in the second cell area; and sequentially forming a dielectric layer and a top electrode on the bottom electrode structure and the dummy structure, wherein the bottom electrode structure includes a plurality of bottom electrodes extending in a first direction in the first cell area and first and second supporters to support the plurality of bottom electrodes, wherein the dummy structure includes a first mold film, a first supporter film, a second mold film, and a second supporter film that are sequentially formed to cover the second cell area, and the second supporter and the second supporter film are at a same level relative to the wafer.

Abstract translation: 制造半导体器件的方法包括：制备其中限定了第一单元区域和第二单元区域的晶片; 在所述第一单元区域中形成底部电极结构，以及位于所述第二单元区域中的虚设结构; 并且在所述底部电极结构和所述虚拟结构上顺序地形成电介质层和顶部电极，其中所述底部电极结构包括在所述第一电池区域中沿第一方向延伸的多个底部电极以及支撑所述多个电极的所述第一和第二支撑件 的底部电极，其中所述虚拟结构包括依次形成以覆盖所述第二电池区域的第一模制膜，第一支撑膜，第二模制膜和第二支撑膜，并且所述第二支撑件和所述第二支撑膜为 在相同的水平相对于晶片。

公开(公告)号：US09659940B2

公开(公告)日：2017-05-23

申请号：US15202874

申请日：2016-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-sung Park ,  In-seak Hwang ,  Bo-un Yoon ,  Byoung-ho Kwon ,  Jong-hyuk Park ,  Jae-hee Kim ,  Myung-jae Jang

IPC: H01L21/20 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/90

Abstract: A method of manufacturing a semiconductor device includes: preparing a wafer in which a first cell area and a second cell area are defined; forming a bottom electrode structure in the first cell area and a dummy structure located in the second cell area; and sequentially forming a dielectric layer and a top electrode on the bottom electrode structure and the dummy structure, wherein the bottom electrode structure includes a plurality of bottom electrodes extending in a first direction in the first cell area and first and second supporters to support the plurality of bottom electrodes, wherein the dummy structure includes a first mold film, a first supporter film, a second mold film, and a second supporter film that are sequentially formed to cover the second cell area, and the second supporter and the second supporter film are at a same level relative to the wafer.