公开(公告)号：US20170084710A1

公开(公告)日：2017-03-23

申请号：US15185253

申请日：2016-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-ho Koh ,  Byoung-ho Kwon ,  Yang-hee Lee ,  Young-kuk Kim ,  In-seak Hwang ,  Bo-un Yoon

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/105 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L21/823475 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10897

Abstract: A semiconductor device including a direct contact and a bit line in a cell array region and a gate electrode structure in a peripheral circuit region, and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate including a cell array region including a first active region and a peripheral circuit region including a second active region, a first insulating layer on the substrate, the first insulating layer including contact holes exposing the first active region, a direct contact in the contact holes, wherein a direct contact is connected to the first active region, a bit line connected to the direct contact in the cell array region and extending in a first direction, and a gate insulating layer and a gate electrode structure, wherein a dummy conductive layer including substantially the same material as the direct contact is in the peripheral circuit region.

公开(公告)号：US10109529B2

公开(公告)日：2018-10-23

申请号：US15185253

申请日：2016-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-ho Koh ,  Byoung-ho Kwon ,  Yang-hee Lee ,  Young-kuk Kim ,  In-seak Hwang ,  Bo-un Yoon

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/108

Abstract: A semiconductor device including a direct contact and a bit line in a cell array region and a gate electrode structure in a peripheral circuit region, and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate including a cell array region including a first active region and a peripheral circuit region including a second active region, a first insulating layer on the substrate, the first insulating layer including contact holes exposing the first active region, a direct contact in the contact holes, wherein a direct contact is connected to the first active region, a bit line connected to the direct contact in the cell array region and extending in a first direction, and a gate insulating layer and a gate electrode structure, wherein a dummy conductive layer including substantially the same material as the direct contact is in the peripheral circuit region.

公开(公告)号：US09831186B2

公开(公告)日：2017-11-28

申请号：US14736455

申请日：2015-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-hyun Park ,  Byoung-ho Kwon ,  Dong-chan Kim ,  Choong-seob Shin ,  Jong-su Kim ,  Bo-un Yoon

IPC: H01L21/66 ,  H01L23/544 ,  H01L21/4757 ,  H01L21/768

CPC classification number: H01L23/544 ,  H01L21/47573 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7684 ,  H01L22/12 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device includes forming a first alignment mark trench in a first material layer on a substrate. A first alignment mark via may then be formed by etching a second material layer that is underneath the first material layer, where the first alignment mark via is positioned to communicate with the first alignment mark trench. Then, a trench-via-merged-type first alignment mark may be formed by filling the first alignment mark trench and the first alignment mark via with a light reflection material layer.

公开(公告)号：US20170077103A1

公开(公告)日：2017-03-16

申请号：US15202874

申请日：2016-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-sung Park ,  ln-seak Hwang ,  Bo-un Yoon ,  Byoung-ho Kwon ,  Jong-hyuk Park ,  Jae-hee Kim ,  Myung-jae Jang

IPC: H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/90

Abstract: A method of manufacturing a semiconductor device includes: preparing a wafer in which a first cell area and a second cell area are defined; forming a bottom electrode structure in the first cell area and a dummy structure located in the second cell area; and sequentially forming a dielectric layer and a top electrode on the bottom electrode structure and the dummy structure, wherein the bottom electrode structure includes a plurality of bottom electrodes extending in a first direction in the first cell area and first and second supporters to support the plurality of bottom electrodes, wherein the dummy structure includes a first mold film, a first supporter film, a second mold film, and a second supporter film that are sequentially formed to cover the second cell area, and the second supporter and the second supporter film are at a same level relative to the wafer.

Abstract translation: 制造半导体器件的方法包括：制备其中限定了第一单元区域和第二单元区域的晶片; 在所述第一单元区域中形成底部电极结构，以及位于所述第二单元区域中的虚设结构; 并且在所述底部电极结构和所述虚拟结构上顺序地形成电介质层和顶部电极，其中所述底部电极结构包括在所述第一电池区域中沿第一方向延伸的多个底部电极以及支撑所述多个电极的所述第一和第二支撑件 的底部电极，其中所述虚拟结构包括依次形成以覆盖所述第二电池区域的第一模制膜，第一支撑膜，第二模制膜和第二支撑膜，并且所述第二支撑件和所述第二支撑膜为 在相同的水平相对于晶片。

公开(公告)号：US09659940B2

公开(公告)日：2017-05-23

申请号：US15202874

申请日：2016-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-sung Park ,  In-seak Hwang ,  Bo-un Yoon ,  Byoung-ho Kwon ,  Jong-hyuk Park ,  Jae-hee Kim ,  Myung-jae Jang

IPC: H01L21/20 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/90

Abstract: A method of manufacturing a semiconductor device includes: preparing a wafer in which a first cell area and a second cell area are defined; forming a bottom electrode structure in the first cell area and a dummy structure located in the second cell area; and sequentially forming a dielectric layer and a top electrode on the bottom electrode structure and the dummy structure, wherein the bottom electrode structure includes a plurality of bottom electrodes extending in a first direction in the first cell area and first and second supporters to support the plurality of bottom electrodes, wherein the dummy structure includes a first mold film, a first supporter film, a second mold film, and a second supporter film that are sequentially formed to cover the second cell area, and the second supporter and the second supporter film are at a same level relative to the wafer.

公开(公告)号：US20160079260A1

公开(公告)日：2016-03-17

申请号：US14729111

申请日：2015-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-woo Bae ,  Byoung-ho Kwon ,  Jong-hyuk Park ,  Hye-sung Park ,  Jun-seok Lee ,  Ki-vin Im ,  Hee-sook Cheon ,  In-seak Hwang

IPC: H01L27/115 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/311 ,  H01L21/31 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/3105

CPC classification number: H01L27/11573 ,  C09G1/02 ,  H01L21/31 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/32051 ,  H01L21/32135 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L27/11582 ,  H01L29/66833

Abstract: A method of fabricating a semiconductor device includes providing a substrate having a cell region and a peripheral circuit region. A plurality of bit line structures are formed on the substrate in the cell region, and a gate structure having the same structure as each of the bit line structures is formed on the substrate in the peripheral circuit region. A spacer is formed on sidewalls of the bit line structures and the gate structure. The bit line structures extend in a first direction and are spaced apart from each other in a second direction that is perpendicular to the first direction by first grooves that extend in the first direction. A sacrificial layer is formed to fill the first grooves and to cover top surfaces of the bit line structures and the gate structure. The sacrificial layer is planarized until the top surfaces of the bit line structures and the gate structure are exposed.

Abstract translation: 制造半导体器件的方法包括提供具有单元区域和外围电路区域的衬底。 在单元区域中的基板上形成多个位线结构，并且在外围电路区域中的基板上形成具有与每个位线结构相同结构的栅极结构。 在位线结构和栅极结构的侧壁上形成间隔物。 位线结构在第一方向上延伸并且在垂直于第一方向的第二方向上通过在第一方向上延伸的第一凹槽彼此间隔开。 形成牺牲层以填充第一凹槽并覆盖位线结构和栅极结构的顶表面。 牺牲层被平坦化，直到位线结构的顶表面和栅极结构被暴露。

公开(公告)号：US09269720B1

公开(公告)日：2016-02-23

申请号：US14729111

申请日：2015-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-woo Bae ,  Byoung-ho Kwon ,  Jong-hyuk Park ,  Hye-sung Park ,  Jun-seok Lee ,  Ki-vin Im ,  Hee-sook Cheon ,  In-seak Hwang

IPC: H01L27/10 ,  H01L27/115 ,  H01L29/66 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/31 ,  H01L21/3213 ,  H01L21/3205

CPC classification number: H01L27/11573 ,  C09G1/02 ,  H01L21/31 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/32051 ,  H01L21/32135 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L27/11582 ,  H01L29/66833

Abstract: A method of fabricating a semiconductor device includes providing a substrate having a cell region and a peripheral circuit region. A plurality of bit line structures are formed on the substrate in the cell region, and a gate structure having the same structure as each of the bit line structures is formed on the substrate in the peripheral circuit region. A spacer is formed on sidewalls of the bit line structures and the gate structure. The bit line structures extend in a first direction and are spaced apart from each other in a second direction that is perpendicular to the first direction by first grooves that extend in the first direction. A sacrificial layer is formed to fill the first grooves and to cover top surfaces of the bit line structures and the gate structure. The sacrificial layer is planarized until the top surfaces of the bit line structures and the gate structure are exposed.

Abstract translation: 制造半导体器件的方法包括提供具有单元区域和外围电路区域的衬底。 在单元区域中的基板上形成多个位线结构，并且在外围电路区域中的基板上形成具有与每个位线结构相同结构的栅极结构。 在位线结构和栅极结构的侧壁上形成间隔物。 位线结构在第一方向上延伸并且在垂直于第一方向的第二方向上通过在第一方向上延伸的第一凹槽彼此间隔开。 形成牺牲层以填充第一凹槽并覆盖位线结构和栅极结构的顶表面。 牺牲层被平坦化，直到位线结构的顶表面和栅极结构被暴露。