公开(公告)号：US20220383938A1

公开(公告)日：2022-12-01

申请号：US17883498

申请日：2022-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pavan Kumar KASIBHATLA ,  Seong-Il O ,  Hak-soo Yu

IPC: G11C11/4091 ,  G11C11/408 ,  G06F15/78 ,  G11C11/4096 ,  G11C7/10 ,  G11C11/4093

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

公开(公告)号：US20210335413A1

公开(公告)日：2021-10-28

申请号：US17369010

申请日：2021-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pavan Kumar KASIBHATLA ,  Seong-il O ,  Hak-soo Yu

IPC: G11C11/4091 ,  G11C11/408 ,  G06F15/78 ,  G11C11/4096 ,  G11C7/10 ,  G11C11/4093

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

公开(公告)号：US20240379150A1

公开(公告)日：2024-11-14

申请号：US18782884

申请日：2024-07-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pavan Kumar KASIBHATLA ,  Seong-il O ,  Hak-soo YU

IPC: G11C11/4091 ,  G06F15/78 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

公开(公告)号：US20230360693A1

公开(公告)日：2023-11-09

申请号：US18223078

申请日：2023-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pavan Kumar KASIBHATLA ,  Seong-il O. ,  Hak-soo YU

IPC: G11C11/4091 ,  G11C11/408 ,  G06F15/78 ,  G11C11/4096 ,  G11C7/10 ,  G11C11/4093

CPC classification number: G11C11/4091 ,  G11C11/4087 ,  G06F15/7821 ,  G11C11/4096 ,  G11C7/1006 ,  G11C11/4093

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

公开(公告)号：US20180081557A1

公开(公告)日：2018-03-22

申请号：US15685084

申请日：2017-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pavan Kumar KASIBHATLA ,  Hak-Soo YU ,  Seokin Hong

IPC: G06F3/06 ,  H04L12/28

CPC classification number: G06F3/0607 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0688 ,  H04L12/28 ,  H04L12/4625

Abstract: Disclosed is a computer system which includes a host and a memory module. The host transfers a plurality of cache lines to a memory module through a plurality of channels, the cache lines including a plurality of data elements and allocates cache lines with target data elements in the plurality of data elements to one channel of the plurality of channels. The target data elements are arranged within the ache lines according to a stride interval. The stride interval is a number of data elements between consecutive ones of the target data elements. The memory module includes gather-scatter engines that are respectively connected to the plurality of channels and scatter or gather the target data elements under control of the host.