公开(公告)号：US12119037B2

公开(公告)日：2024-10-15

申请号：US17937120

申请日：2022-09-30

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Jixing Chen

IPC: G11C11/406 ,  G11C11/408 ,  H03K19/20

CPC classification number: G11C11/406 ,  G11C11/4087 ,  H03K19/20

Abstract: A refresh circuit includes a refresh counter configured to output address signals through a plurality of address pins; an address mixer configured to output row address selection signals according to the address signals received by the row address pins, output first bank address signals according to the address signals received by bank address pins, receive a refresh signal and a power supply voltage signal, and output fixed second bank address signals according to the refresh signal and the power supply voltage signal; and an address pre-decoding circuit configured to output a preset number of bank address selection signals according to the first bank address signals and the second bank address signals.

公开(公告)号：US12094514B2

公开(公告)日：2024-09-17

申请号：US17884053

申请日：2022-08-09

Applicant: Winbond Electronics Corp.

Inventor： Chih-Chiang Lai

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G11C11/40611 ,  G11C11/4085 ,  G11C11/4087 ,  G11C2211/4067

Abstract: A memory device coupled to a memory controller and including a memory array and an access circuit is provided. The memory array includes a plurality of cells. Each of the cells is coupled to a word-line. The access circuit is coupled between the memory controller and the memory array. In a normal mode, the access circuit executes a refresh action for the cells which are coupled to at least one word-line in response to the memory controller outputting an auto-refresh command. In a standby mode, the access circuit selects one of the word-lines and determines whether to execute the refresh action for the cells coupled to the selected word-line according to the retention capability of the selected word-line at regular time intervals.

公开(公告)号：US12087350B2

公开(公告)日：2024-09-10

申请号：US17032191

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： William Waller ,  Cheng-Yi Huang

IPC: G11C11/408 ,  G11C5/02 ,  G11C5/06 ,  G11C11/4094

CPC classification number: G11C11/4087 ,  G11C5/025 ,  G11C5/06 ,  G11C11/4085 ,  G11C11/4094

Abstract: Systems, apparatuses and methods may provide for a multi-deck non-volatile memory architecture with an improved wordline bus and bitline bus configuration. For example, wordline busses and bitline busses may be positioned so as to be located over the junctions between two tiles, e.g., between a memory tile and a termination tile and between two memory tiles. Additionally, multi-deck non-volatile memory architectures may utilize data shifting to select which one of a plurality of wordline drivers and a plurality of bitline drivers are in communication with a data circuit of each memory tile. In a configuration where wordline busses and bitline busses have been positioned so as to be located over the junctions between two tiles, such data shifting directions may be able to be implemented with a limited number of shifting direction.

公开(公告)号：US20240282355A1

公开(公告)日：2024-08-22

申请号：US18649696

申请日：2024-04-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Nathaniel J. Meier ,  Michael A. Shore

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/40622 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4087

Abstract: Apparatuses, systems, and methods for controller directed targeted refresh operations. A memory may be coupled to a controller. The memory may identify aggressor addresses based on sampled addresses. The addresses may be sampled based on internal timing logic of the memory and also based on a sampling command received from the controller. The memory may also receive a controller identified aggressor address from the controller. The memory may refresh one or more victim word lines of the identified (either by the memory or the controller) aggressor addresses as part of a targeted refresh operation. Victims of controller identified aggressor addresses may be refreshed before memory identified aggressor addresses.

公开(公告)号：US20240281326A1

公开(公告)日：2024-08-22

申请号：US18357930

申请日：2023-07-24

Applicant: SK hynix Inc.

Inventor： Yong Wan HWANG ,  Tae Woong HA ,  Kwang Ho CHOI ,  Moon Hyeok CHOI

IPC: G06F11/10 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G06F11/1068 ,  G11C11/4087 ,  G11C11/4091

Abstract: A memory module includes a plurality of first memory chips and a second memory chip. Raw data is stored in the plurality of first memory chips. Parity data generated based on the raw data is stored in the second memory chip. Each of the first memory chips and the second memory chip is configured to exchange data with a controller based on a burst length unit. The second memory chip stores a first parity data generated from the raw data by a first error correction method, and stores a second parity data generated from the raw data and the first parity data by a second error correction method.

公开(公告)号：US12057184B2

公开(公告)日：2024-08-06

申请号：US18164100

申请日：2023-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghye Cho ,  Kiheung Kim ,  Sungrae Kim ,  Junhyung Kim ,  Kijun Lee ,  Myungkyu Lee ,  Changyong Lee ,  Sanguhn Cha

IPC: G11C29/42 ,  G11C11/408 ,  G11C11/4091 ,  G11C29/44 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C11/4087 ,  G11C11/4091 ,  G11C29/4401 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A memory system includes a memory module having a plurality of memory devices therein. A memory controller is configured to transmit commands and addresses to the memory module in synchronization with a clock, input/output data to and from the memory module in synchronization with a data transfer clock, and perform system error correction operations on data read from the memory module. The plurality of memory devices perform on-die error correction operations, which are different from each other according to a physical location of the stored read data.

公开(公告)号：US20240257841A1

公开(公告)日：2024-08-01

申请号：US18634074

申请日：2024-04-12

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Baekkyu Choi

IPC: G11C5/06 ,  G06F13/16 ,  G11C11/22 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/56

CPC classification number: G11C5/063 ,  G06F13/1668 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/4091 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/4087 ,  G11C11/565 ,  G11C11/5657

Abstract: Methods and devices for dynamic allocation of a capacitive component in a memory device are described. A memory device may include one or more voltage rails for distributing supply voltages to a memory die. A memory device may include a capacitive component that may be dynamically coupled to a voltage rail based on an identification of an operating condition on the memory die, such as a voltage droop on the voltage rail. The capacitive component may be dynamically coupled with the voltage rail to maintain the supply voltage on the voltage rail during periods of high demand. The capacitive component may be dynamically switched between voltage rails during operation of the memory device based on operating conditions associated with the voltage rails.

公开(公告)号：US12046675B2

公开(公告)日：2024-07-23

申请号：US18234043

申请日：2023-08-15

Applicant: Zeno Semiconductor, Inc.

Inventor： Jin-Woo Han ,  Dinesh Maheshwari ,  Yuniarto Widjaja

IPC: H10B12/00 ,  H01L27/12 ,  H01L29/78 ,  G06F11/10 ,  G11C7/02 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/12 ,  G11C29/52

CPC classification number: H01L29/7841 ,  H01L27/1211 ,  H10B12/20 ,  G06F11/1068 ,  G11C7/02 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4096 ,  G11C29/12 ,  G11C29/52 ,  H01L29/785

Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

公开(公告)号：US20240242758A1

公开(公告)日：2024-07-18

申请号：US18421741

申请日：2024-01-24

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Stefan Frederik Schippers

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4091 ,  H10B12/00 ,  G11C11/56

CPC classification number: G11C11/4096 ,  G11C11/4085 ,  G11C11/4091 ,  H10B12/30 ,  H10B12/50 ,  G11C11/4087 ,  G11C11/565

Abstract: Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.

公开(公告)号：US20240233802A9

公开(公告)日：2024-07-11

申请号：US18295285

申请日：2023-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongpil Son

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40618 ,  G11C11/40615 ,  G11C11/4087

Abstract: Disclosed is a semiconductor memory device that includes a memory cell array including a plurality of memory banks, a command decoder configured to decode a per-bank refresh command and a remaining bank refresh command received from an external source, and a refresh controller configured to control the cell array to perform a per-bank refresh operation for refreshing one memory bank among the plurality of memory banks that is based on a decoding result of the per-bank refresh command of the command decoder, wherein the refresh controller is configured to perform a remaining bank refresh operation for refreshing remaining memory banks other than the one memory bank among the plurality of memory banks, in response to the remaining bank refresh command during one refresh cycle.