公开(公告)号：US20220130761A1

公开(公告)日：2022-04-28

申请号：US17374713

申请日：2021-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaechoon Kim ,  Seunggeol Ryu ,  Kyungsuk Oh ,  Keungbeum Kim ,  Eonsoo Jang

IPC: H01L23/528 ,  H01L23/48 ,  H01L23/522 ,  H01L23/36 ,  H01L23/00

Abstract: An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to the upper via; a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers.

公开(公告)号：US12009303B2

公开(公告)日：2024-06-11

申请号：US17374713

申请日：2021-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaechoon Kim ,  Seunggeol Ryu ,  Kyungsuk Oh ,  Keungbeum Kim ,  Eonsoo Jang

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/36 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/08 ,  H01L2224/08145

Abstract: An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to the upper via; a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers.

公开(公告)号：US12237268B2

公开(公告)日：2025-02-25

申请号：US18660550

申请日：2024-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaechoon Kim ,  Seunggeol Ryu ,  Kyungsuk Oh ,  Keungbeum Kim ,  Eonsoo Jang

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/36 ,  H01L23/48 ,  H01L23/522

Abstract: An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to the upper via; a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers.

公开(公告)号：US11935812B2

公开(公告)日：2024-03-19

申请号：US17209974

申请日：2021-03-23

Applicant: Samsung Electronics Co., Ltd. ,  UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITY

Inventor： Seunggeol Ryu ,  Seokkan Ki ,  Youngsuk Nam ,  Jaechoon Kim ,  Bangweon Lee ,  Seungtae Hwang

IPC: H01L23/373 ,  H01L23/473

CPC classification number: H01L23/3736 ,  H01L23/473

Abstract: A semiconductor package may include a package substrate, a semiconductor chip on the package substrate, a heat dissipation member on the semiconductor chip, and a first thermal interface material coated on an upper surface of the semiconductor chip to bond the semiconductor chip and the heat dissipation member. The first thermal interface material may include a liquid metal and fine particles disposed inside the liquid metal. The fine particles may have no oxide layer on a surface thereof. A volume percentage of the fine particles in the liquid metal including the fine particles therein may be about 1% to about 5%. A thermal conductivity of the liquid metal including the fine particles therein may be equal to or more than about 40 W/m·K.

公开(公告)号：US20250157930A1

公开(公告)日：2025-05-15

申请号：US19028311

申请日：2025-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaechoon Kim ,  Seunggeol Ryu ,  Kyungsuk Oh ,  Keungbeum Kim ,  Eonsoo Jang

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/36 ,  H01L23/48 ,  H01L23/522

Abstract: An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to the upper via; a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers.

公开(公告)号：US12243803B2

公开(公告)日：2025-03-04

申请号：US18437385

申请日：2024-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol Ryu ,  Seokkan Ki ,  Youngsuk Nam ,  Jaechoon Kim ,  Bangweon Lee ,  Seungtae Hwang

IPC: H01L23/373 ,  H01L23/473

Abstract: A method of manufacturing a thermal interface material may include mixing fine particles with an acidic solution to remove a first oxide layer from a surface of each of the fine particles, injecting a liquid metal into the acidic solution to remove a second oxide layer from a surface of the liquid metal and for the fine particles from which the first oxide layer is removed in the acidic solution to penetrate into the liquid metal from which the second oxide layer is remove, and extracting the liquid metal including the fine particles therein from the acidic solution.

公开(公告)号：US20240290720A1

公开(公告)日：2024-08-29

申请号：US18660550

申请日：2024-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaechoon Kim ,  Seunggeol Ryu ,  Kyungsuk Oh ,  Keungbeum Kim ,  Eonsoo Jang

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/36 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/08 ,  H01L2224/08145

Abstract: An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising a bonding pad connected to the upper via; a power delivery network-level portion arranged under the second surface of the substrate and comprising a plurality of lower multi-layer interconnect layers connected to the rail through via and lower vias connecting the lower multi-layer interconnect layers to each other; and an external connection terminal arranged under the power delivery network-level portion and connected to the lower multi-layer interconnect layers.

公开(公告)号：US20240186215A1

公开(公告)日：2024-06-06

申请号：US18437385

申请日：2024-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol Ryu ,  Seokkan Ki ,  Youngsuk Nam ,  Jaechoon Kim ,  Bangweon Lee ,  Seungtae Hwang

IPC: H01L23/373 ,  H01L23/473

CPC classification number: H01L23/3736 ,  H01L23/473

Abstract: A method of manufacturing a thermal interface material may include mixing fine particles with an acidic solution to remove a first oxide layer from a surface of each of the fine particles, injecting a liquid metal into the acidic solution to remove a second oxide layer from a surface of the liquid metal and for the fine particles from which the first oxide layer is removed in the acidic solution to penetrate into the liquid metal from which the second oxide layer is remove, and extracting the liquid metal including the fine particles therein from the acidic solution.