公开(公告)号：US20240363590A1

公开(公告)日：2024-10-31

申请号：US18767207

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Chung-Hao Tsai ,  Chuei-Tang Wang

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L21/566 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2924/1434

摘要： A method includes thinning a semiconductor substrate of a device die to reveal through-substrate vias that extend into the semiconductor substrate, and forming a first redistribution structure, which includes forming a first plurality of dielectric layers over the semiconductor substrate, and forming a first plurality of redistribution lines in the first plurality of dielectric layers. The first plurality of redistribution lines are electrically connected to the through-substrate vias. The method further includes placing a first memory die over the first redistribution structure, and forming a first plurality of metal posts over the first redistribution structure. The first plurality of metal posts are electrically connected to the first plurality of redistribution lines. The first memory die is encapsulated in a first encapsulant. A second plurality of redistribution lines are formed over, and electrically connected to, the first plurality of metal posts and the first memory die.

公开(公告)号：US20240363536A1

公开(公告)日：2024-10-31

申请号：US18634187

申请日：2024-04-12

申请人： Samsung Electronics Co., Ltd.

发明人： Jinyoung PARK ,  Heonjong SHIN ,  Jaehyun KANG ,  Youngsoo SONG

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L23/5286 ,  H01L21/76898 ,  H01L21/823871 ,  H01L23/481 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： A semiconductor device may include a substrate including a first active region including first active patterns spaced apart by a first interval, a second active region including second active patterns spaced apart by a second interval, first and second source/drain regions on the first and second active regions, first and second contact structures connected to the first and second source/drain regions, first and second conductive through-structures connected to the first and second contact structures, a power delivery structure in contact with bottom surfaces of the first and second conductive through-structures, a frontside interconnection structure, and a backside interconnection structure. The first conductive through-structure may be connected to the first source/drain region through the first contact structure. The second conductive through-structure may be connected to the second source/drain region through the frontside interconnection structure. The second interval may be different than the first interval.

公开(公告)号：US20240363493A1

公开(公告)日：2024-10-31

申请号：US18524812

申请日：2023-11-30

申请人： Samsung Electronics Co., Ltd.

发明人： Duckseoung KANG ,  Sangdeok KWON ,  Gibum KIM

IPC分类号： H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： A semiconductor device may include a semiconductor substrate, a channel pattern on a first surface of the semiconductor substrate, source/drain patterns on the first surface of the semiconductor substrate and on both sides of the channel pattern, a contact electrode electrically connected to the source/drain patterns, a lower wiring structure on the second surface of the semiconductor substrate, and a through via penetrating the semiconductor substrate and connecting the contact electrode and the lower wiring structure to each other. The lower wiring structure may include a first metal line connected to a first voltage, a second metal line connected to a second voltage, and an auxiliary electrode electrically connected to one of the first metal line and the second metal line. The auxiliary electrode may overlap and be insulated from an other of the first metal line and the second metal line.

公开(公告)号：US20240363490A1

公开(公告)日：2024-10-31

申请号：US18140146

申请日：2023-04-27

申请人： Intel Corporation

发明人： Mohammad Enamul KABIR ,  Keith ZAWADZKI ,  Rahim KASIM ,  Sunny CHUGH ,  Zhizheng ZHANG ,  Christopher M. PELTO ,  Babita DHAYAL ,  John Kevin TAYLOR ,  Doug INGERLY

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L23/58 ,  H01L29/06

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/49827 ,  H01L23/585 ,  H01L24/16 ,  H01L29/0619 ,  H01L2224/16225

摘要： Through-silicon via dies are described. In an example, a semiconductor die includes a substrate having a device side and a backside. An active device layer is in or on the device side of the substrate. A dielectric structure is over the active device layer. A first die-edge metal guard ring is in the dielectric structure and around an outer perimeter of the substrate. A plurality of metallization layers is in the dielectric structure and within the first die-edge metal guard ring. A plurality of through silicon vias is in the substrate and extend into the dielectric structure and are connected to the plurality of metallization layers. A plurality of backside metallization structures is beneath the backside of the substrate. The plurality of through silicon vias are connected to the plurality of backside metallization structures. A second die-edge metal guard ring is laterally around the plurality of backside metallization structures.

公开(公告)号：US20240363489A1

公开(公告)日：2024-10-31

申请号：US18754081

申请日：2024-06-25

申请人： Yibu Semiconductor Co., Ltd.

发明人： Ming Li

IPC分类号： H01L23/473 ,  H01L21/304 ,  H01L21/306 ,  H01L21/308 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18 ,  H10B80/00

CPC分类号： H01L23/473 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/308 ,  H01L23/481 ,  H01L24/80 ,  H01L24/08 ,  H01L24/16 ,  H01L25/18 ,  H01L2224/08146 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/1431 ,  H01L2924/1436 ,  H10B80/00

摘要： The present disclosure relates to a chip stack in the semiconductor field and a method of manufacturing the same. The chip stack comprises a plurality of stacked chips, the active surface of a first chip of the plurality of chips facing the passive surface of a second chip immediately below the first chip, and at least one open cavity embedded in the passive surface of the second chip forming a closed micro-channel with the active surface of the first chip. The microchannels in the stacked chips allow cooling micro-fluid to be introduced into the microchannels. The micro-fluid can flow from one chip to another, taking away heat generated by the chips, allowing heat dissipation of the chip stack to meet industry requirement. The micro-channels for dissipating the heat are formed while the chips are stacked. Thus, besides forming the micro-channels, no additional process steps are required to form the chip stack.

公开(公告)号：US20240363458A1

公开(公告)日：2024-10-31

申请号：US18309408

申请日：2023-04-28

申请人： Joon Bu Park

发明人： Joon Bu Park

IPC分类号： H01L23/15 ,  H01L23/14 ,  H01L23/29 ,  H01L23/48 ,  H01L25/065

CPC分类号： H01L23/15 ,  H01L23/147 ,  H01L23/291 ,  H01L23/481 ,  H01L25/0657 ,  H01L2225/06565 ,  H01L2225/06589

摘要： A circuit chip includes a first body having a negative Poisson's ratio; a second body having a positive Poisson's ratio, wherein the first body and the second body are stacked on one another and thermally coupled to one another; and a first integrated circuit embedded in the second body.

公开(公告)号：US20240363385A1

公开(公告)日：2024-10-31

申请号：US18736423

申请日：2024-06-06

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC分类号： H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/525 ,  H01L25/00 ,  H01L25/065 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B20/20 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

CPC分类号： H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

摘要： A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer, a third level including third transistors and overlaying the second level, a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit.

公开(公告)号：US20240363366A1

公开(公告)日：2024-10-31

申请号：US18771181

申请日：2024-07-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chien-Hsun Chen ,  Yu-Min Liang ,  Yen-Ping Wang ,  Jiun Yi Wu ,  Chen-Hua Yu ,  Kai-Chiang Wu

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522

CPC分类号： H01L21/486 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/5226

摘要： Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

公开(公告)号：US12131976B2

公开(公告)日：2024-10-29

申请号：US17037542

申请日：2020-09-29

申请人： UNITED MICROELECTRONICS CORP.

发明人： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC分类号： H01L23/36 ,  H01L21/768 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/48 ,  H01L23/485 ,  H01L25/00 ,  H01L25/07

CPC分类号： H01L23/3677 ,  H01L21/76898 ,  H01L23/3735 ,  H01L23/481 ,  H01L23/485 ,  H01L24/08 ,  H01L24/32 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/32145 ,  H01L2224/32225

摘要： A semiconductor structure with a heat dissipation structure includes a first device wafer includes a front side and a back side. A first transistor is disposed on the front side. The first transistor includes a first gate structure disposed on the front side. Two first source/drain doping regions are embedded within the first device wafer at two side of the first gate structure. A channel region is disposed between the two first source/drain doping regions and embedded within the first device wafer. A first dummy metal structure contacts the back side of the first device wafer, and overlaps the channel region.

公开(公告)号：US12131898B2

公开(公告)日：2024-10-29

申请号：US17745182

申请日：2022-05-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jing-Cheng Lin

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L21/822 ,  H01L23/48 ,  H01L27/06

CPC分类号： H01L21/02104 ,  H01L21/8221 ,  H01L27/0688 ,  H01L21/2007 ,  H01L21/76254 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided that includes operations as follows: bonding an epitaxial layer formed with a first semiconductor substrate and an ion-implanted layer that is formed between the epitaxial layer and the first semiconductor substrate, to a bonding oxide layer of a second semiconductor substrate; separating the first semiconductor substrate from the epitaxial layer, by removing the first semiconductor substrate together with a portion of the ion-implanted layer and keeping the epitaxial layer; and forming a first semiconductor device portion on the epitaxial layer, and an interconnect layer on the first semiconductor device portion.