公开(公告)号：US20240201256A1

公开(公告)日：2024-06-20

申请号：US18538692

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sumin Noh ,  Yongki Lee ,  Jieun Park ,  Yunhyeok Choi ,  Bohdan Karpinskyy

IPC: G01R31/3177 ,  H04L9/32

CPC classification number: G01R31/3177 ,  H04L9/3278

Abstract: A device is provided. The device includes: a plurality of physically unclonable function (PUF) cells, each of the plurality of PUF cells including at least one logic gate and being configured to generate an output signal based on at least one threshold level of the at least one logic gate; a signal generator configured to generate an input signal that is provided to each of the plurality of PUF cells; and a controller configured to, in a test mode, generate a control signal to control the signal generator to vary the input signal to control the plurality of PUF cells to output a plurality of output signals according to the input signal, and identify at least one weak PUF cell from among the plurality of PUF cells based on the output signal generated by the at least one weak PUF cell being an unstable output signal. The controller is further configured to disconnect the plurality of PUF cells from the signal generator in a normal mode.

公开(公告)号：US20230153069A1

公开(公告)日：2023-05-18

申请号：US17944486

申请日：2022-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jieun Park ,  Yongki Lee ,  Sumin Noh ,  Yunhyeok Choi ,  Bohdan Karpinskyy

IPC: G06F7/58

CPC classification number: G06F7/58

Abstract: A random number generator according to example embodiments includes an initial random number generator configured to generate an initial random number, a self-timed ring (STR) oscillator configured to receive the initial random number, the STR oscillator having a plurality of ring stages generating, in response to a clock, either a bubble that does not change an output state of a previous clock or a token changing the output state of the previous clock, a duty corrector configured to adjust a duty of each of output values of the ring stages, and a sampling circuit configured to sample a random number using a logic operation from the duty-corrected output values.