公开(公告)号：US11277272B2

公开(公告)日：2022-03-15

申请号：US16567751

申请日：2019-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunhyeok Choi ,  Yongki Lee ,  Yongsoo Kim ,  Jieun Park ,  Bohdan Karpinskyy

IPC: H04L9/00 ,  H04L9/32 ,  H04L9/08

Abstract: Systems and methods are described based on an integrated circuit that performs a challenge-response physically unclonable function (PUF). The PUF is used for challenge-response authentication. The integrated circuit includes a PUP block configured to output an n-bit internal response corresponding to a challenge that requests a response where n is an integer greater than 1 and a response generator configured to calculate a Hamming weight of the internal response and output the response by comparing the Hamming weight with at least one reference.

公开(公告)号：US20240136201A1

公开(公告)日：2024-04-25

申请号：US18381905

申请日：2023-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuseon HEO ,  Junhyeong Park ,  Jieun Park ,  Jihye Shim ,  Jiyoung Lee

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L21/4857 ,  H01L23/3128 ,  H01L23/49838 ,  H01L25/18 ,  H10B80/00 ,  H01L24/04

Abstract: Provided is a method of manufacturing a semiconductor package, the method including forming a first wiring structure, coating a high transmittance photoresist on the first wiring structure a plurality of number of times, forming a plurality of openings by exposing and developing the high transmittance photoresist, forming a plurality of conductive posts by filling the plurality of openings with a conductive material, removing the high transmittance photoresist, disposing a semiconductor chip on the first wiring structure, forming an encapsulant surrounding the semiconductor chip and the plurality of conductive posts, and forming a second wiring structure on the encapsulant, wherein the light transmittance of the high transmittance photoresist at a portion where the first wiring structure and the high transmittance photoresist contact each other is greater than or equal to 3.2%.

公开(公告)号：US20240234165A9

公开(公告)日：2024-07-11

申请号：US18381905

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuseon HEO ,  Junhyeong Park ,  Jieun Park ,  Jihye Shim ,  Jiyoung Lee

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L21/4857 ,  H01L23/3128 ,  H01L23/49838 ,  H01L25/18 ,  H10B80/00 ,  H01L24/04

Abstract: Provided is a method of manufacturing a semiconductor package, the method including forming a first wiring structure, coating a high transmittance photoresist on the first wiring structure a plurality of number of times, forming a plurality of openings by exposing and developing the high transmittance photoresist, forming a plurality of conductive posts by filling the plurality of openings with a conductive material, removing the high transmittance photoresist, disposing a semiconductor chip on the first wiring structure, forming an encapsulant surrounding the semiconductor chip and the plurality of conductive posts, and forming a second wiring structure on the encapsulant, wherein the light transmittance of the high transmittance photoresist at a portion where the first wiring structure and the high transmittance photoresist contact each other is greater than or equal to 3.2%.

公开(公告)号：US20230153069A1

公开(公告)日：2023-05-18

申请号：US17944486

申请日：2022-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jieun Park ,  Yongki Lee ,  Sumin Noh ,  Yunhyeok Choi ,  Bohdan Karpinskyy

IPC: G06F7/58

CPC classification number: G06F7/58

Abstract: A random number generator according to example embodiments includes an initial random number generator configured to generate an initial random number, a self-timed ring (STR) oscillator configured to receive the initial random number, the STR oscillator having a plurality of ring stages generating, in response to a clock, either a bubble that does not change an output state of a previous clock or a token changing the output state of the previous clock, a duty corrector configured to adjust a duty of each of output values of the ring stages, and a sampling circuit configured to sample a random number using a logic operation from the duty-corrected output values.

公开(公告)号：US11651071B2

公开(公告)日：2023-05-16

申请号：US17003313

申请日：2020-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bohdan Karpinskyy ,  Mijung Noh ,  Jieun Park ,  Yongki Lee ,  Juyeon Lee

IPC: G06F21/55 ,  G06F7/58 ,  H03K3/84 ,  H03K19/20 ,  H03K19/21

CPC classification number: G06F21/552 ,  G06F7/582 ,  G06F7/588 ,  H03K3/84 ,  G06F2221/034 ,  H03K19/20 ,  H03K19/21

Abstract: An apparatus includes an integrated circuit and a plurality of conducting wires disposed on the integrated circuit. The integrated circuit includes: (i) a signal generation circuit, which is configured to generate random signal and selection signal based on random or pseudo-random numbers, (ii) a transmitting circuit configured to select at least one from among the plurality of conducting wires based on the selection signal and to output the random signal through the at least one conducting wire, and (iii) a receiving circuit configured to detect an invasive attack on the integrated circuit based on signal received through the at least one conducting wire.

公开(公告)号：US11329004B2

公开(公告)日：2022-05-10

申请号：US16591119

申请日：2019-10-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jieun Park

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

Abstract: A semiconductor package includes a connection structure having including a plurality of insulating layers and redistribution layers on the plurality of insulating layers. A semiconductor chip has connection pads connected to the redistribution layers, and an encapsulant encapsulates the semiconductor chip. A passive component is embedded in the connection structure and has connection terminals connected to the redistribution layer. The redistribution layers include a plurality of redistribution patterns, each disposed on the plurality of insulating layers and a plurality of redistribution vias each penetrating through the plurality of insulating layers and connected to the plurality of redistribution patterns. The plurality of redistribution vias include a plurality of blocking vias arranged to surround the passive component, and the plurality of redistribution patterns include a blocking pattern connected to adjacent blocking vias.

公开(公告)号：US09753771B2

公开(公告)日：2017-09-05

申请号：US14721517

申请日：2015-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyeongtaek Lee ,  Seungkyu Kim ,  Jieun Park ,  WonJoon Jang

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06F9/4856 ,  G06F9/5027 ,  G06F9/5033 ,  G06F9/5094 ,  Y02D10/22 ,  Y02D10/24 ,  Y02D10/32

Abstract: A scheduling method of a system-on-chip including a multi-core processor includes detecting a scheduling request of a thread to be executed in the multi-core processor, and detecting a calling thread having the same context as the scheduling-requested thread among threads that are being executed in the multi-core processor. The method includes reassigning or resetting the scheduling-requested thread according to performance of a core to execute the calling thread having the same context.

公开(公告)号：US20250125247A1

公开(公告)日：2025-04-17

申请号：US18779913

申请日：2024-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeean Lee ,  Dongwon Kang ,  Jieun Park ,  Changyeon Song ,  Sunguk Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

Abstract: An IC package includes a lower redistribution structure, a connection structure (with cavity) on the lower redistribution structure, a semiconductor chip in the cavity, a molding layer filling the cavity, covering the connection structure and the semiconductor chip, and having an upper through hole therein. An upper redistribution structure is provided that includes: an upper insulating layer on the molding layer, a first protrusion inside the upper through hole, and an upper redistribution pattern, which includes a first upper via pattern, inside the first protrusion. The upper through hole of the molding layer is located above the via structure of the connection structure, the first upper via pattern is electrically connected to the via structure of the connection structure, and a portion of the first upper line pattern of the upper redistribution structure is buried in the upper insulating layer.

公开(公告)号：US20240201256A1

公开(公告)日：2024-06-20

申请号：US18538692

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sumin Noh ,  Yongki Lee ,  Jieun Park ,  Yunhyeok Choi ,  Bohdan Karpinskyy

IPC: G01R31/3177 ,  H04L9/32

CPC classification number: G01R31/3177 ,  H04L9/3278

Abstract: A device is provided. The device includes: a plurality of physically unclonable function (PUF) cells, each of the plurality of PUF cells including at least one logic gate and being configured to generate an output signal based on at least one threshold level of the at least one logic gate; a signal generator configured to generate an input signal that is provided to each of the plurality of PUF cells; and a controller configured to, in a test mode, generate a control signal to control the signal generator to vary the input signal to control the plurality of PUF cells to output a plurality of output signals according to the input signal, and identify at least one weak PUF cell from among the plurality of PUF cells based on the output signal generated by the at least one weak PUF cell being an unstable output signal. The controller is further configured to disconnect the plurality of PUF cells from the signal generator in a normal mode.

公开(公告)号：US11977338B2

公开(公告)日：2024-05-07

申请号：US17340267

申请日：2021-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jieun Park ,  Youngmin Seo ,  Inbeom Yim

IPC: G03F7/00 ,  H01L21/66

CPC classification number: G03F7/70641 ,  G03F7/70683 ,  H01L22/20

Abstract: A method of manufacturing a semiconductor device includes selecting a diffraction based focus (DBF) mark that is unaffected by a pattern of a lower layer; manufacturing a mask including a mark pattern for forming the DBF mark; forming the DBF mark in a cell region of a wafer by using the mask; measuring the DBF mark and monitoring defocus; correcting the defocus on the basis of a result of the monitoring; and forming a pattern in the cell region of the wafer, after correcting the defocus.