公开(公告)号：US20180308856A1

公开(公告)日：2018-10-25

申请号：US15832756

申请日：2017-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunghan Cho ,  Shinhwan Kang

IPC: H01L27/11565 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11582

CPC classification number: H01L27/11565 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53271 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/0847

Abstract: A stack structure including a plurality of gate electrodes is vertically stacked on a substrate and extends in a first direction. A channel structure includes vertical channels penetrating the stack structure and a horizontal channel connecting the vertical channels. The horizontal channel are provided under the stack structure. First lower wiring patterns are disposed between the substrate and the stack structure and electrically connected to the channel structure. Each first lower wiring pattern includes a first portion and a second portion having different widths from each other in the first direction.

公开(公告)号：US10950619B2

公开(公告)日：2021-03-16

申请号：US16223894

申请日：2018-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Jin Jung ,  Sunghan Cho

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/423 ,  H01L27/1157

Abstract: A semiconductor memory device includes a substrate including a cell array region and a pad region, a stack structure disposed on the cell array region and the pad region of the substrate and including gate electrodes, a device isolation layer vertically overlapping the stack structure and disposed in the pad region of the substrate, a dummy vertical channel portion penetrating the stack structure on the pad region of the substrate and disposed in the device isolation layer, and a dummy semiconductor pillar disposed between the dummy vertical channel portion and one portion of the substrate being in contact with one sidewall of the device isolation layer.

公开(公告)号：US10177164B2

公开(公告)日：2019-01-08

申请号：US15832756

申请日：2017-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunghan Cho ,  Shinhwan Kang

IPC: H01L27/115 ,  H01L27/11565 ,  H01L23/532 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11582 ,  H01L23/522 ,  H01L29/08

Abstract: A stack structure including a plurality of gate electrodes is vertically stacked on a substrate and extends in a first direction. A channel structure includes vertical channels penetrating the stack structure and a horizontal channel connecting the vertical channels. The horizontal channel are provided under the stack structure. First lower wiring patterns are disposed between the substrate and the stack structure and electrically connected to the channel structure. Each first lower wiring pattern includes a first portion and a second portion having different widths from each other in the first direction.