公开(公告)号：US09419011B2

公开(公告)日：2016-08-16

申请号：US14588506

申请日：2015-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunyeong Lee ,  Kyoung-Hoon Kim ,  Jin-Woo Park ,  SeungWoo Paek ,  Seok-won Lee ,  Taekeun Cho

IPC: H01L27/00 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L2224/32145

Abstract: Three-dimensional (3D) semiconductor devices are provided. The 3D semiconductor device includes a plurality of dummy pillars penetrating each cell pad of an electrode structure and the electrode structure disposed under each cell pad. Insulating patterns of a mold stack structure for formation of the electrode structure may be supported by the plurality of dummy pillars, so transformation and contact of the insulating patterns may be minimized or prevented.

Abstract translation: 提供三维（3D）半导体器件。 3D半导体器件包括穿过电极结构的每个电池衬垫的多个虚拟柱和设置在每个电池衬垫下方的电极结构。 用于形成电极结构的模具堆叠结构的绝缘图案可以由多个虚拟支柱支撑，因此可以最小化或防止绝缘图案的变形和接触。

公开(公告)号：US11164636B2

公开(公告)日：2021-11-02

申请号：US16898533

申请日：2020-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyeong Lee ,  Kyungmoon Kim ,  Woojae Jang ,  Chanjong Ju

IPC: G11C7/00 ,  G11C16/16 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/34 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04

Abstract: A nonvolatile memory device includes a memory cell array, an erase body voltage generator, and an erase source voltage generator. The memory cell array includes memory blocks, each of which includes cell strings each including a ground selection transistor, memory cells, and a string selection transistor stacked in a direction perpendicular to a substrate. The erase body voltage generator applies an erase body voltage to the substrate during an erase operation. The erase source voltage generator applies an erase source voltage to a common source line connected with ground selection transistors of the cell strings during the erase operation.

公开(公告)号：US10699789B2

公开(公告)日：2020-06-30

申请号：US16177479

申请日：2018-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyeong Lee ,  Kyungmoon Kim ,  Woojae Jang ,  Chanjong Ju

IPC: G11C7/00 ,  G11C16/16 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/34 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04

Abstract: A nonvolatile memory device includes a memory cell array, an erase body voltage generator, and an erase source voltage generator. The memory cell array includes memory blocks, each of which includes cell strings each including a ground selection transistor, memory cells, and a string selection transistor stacked in a direction perpendicular to a substrate. The erase body voltage generator applies an erase body voltage to the substrate during an erase operation. The erase source voltage generator applies an erase source voltage to a common source line connected with ground selection transistors of the cell strings during the erase operation.