公开(公告)号：US20240057328A1

公开(公告)日：2024-02-15

申请号：US17819575

申请日：2022-08-12

申请人： Micron Technology, Inc.

发明人： Umberto Maria Meotto ,  Anna Maria Conti ,  Paolo Tessariol

IPC分类号： H01L27/11524 ,  H01L27/11582 ,  H01L27/11551

CPC分类号： H01L27/11524 ,  H01L27/11582 ,  H01L27/11551 ,  H01L29/0649

摘要： A microelectronic device includes a stack structure including tiers each including insulative material and conductive material vertically adjacent the insulative material. The stack structure divided into at least two blocks separated from one another. The microelectronic device further includes at least one slot structure horizontally interposed between the at least two blocks of the stack structure. The at least one slot structure including additional insulative material and at least one contact structure extending through the additional insulative material to source tier underlying the stack structure.

公开(公告)号：US20230361031A1

公开(公告)日：2023-11-09

申请号：US17738786

申请日：2022-05-06

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Lei LIU ,  Yuancheng Yang ,  Wenxi Zhou ,  Kun Zhang ,  Di Wang ,  Tao Yang ,  Dongxue Zhao ,  Zhiliang Xia ,  Zongliang Huo

IPC分类号： H01L23/528 ,  H01L27/11551 ,  H01L27/11578

CPC分类号： H01L23/5283 ,  H01L27/11551 ,  H01L27/11578

摘要： Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a dielectric stack on the bottom conductive layer, the dielectric stack comprising a plurality of alternatively arranged first dielectric layers and second dielectric layers; forming an opening penetrating the dielectric stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and replacing the plurality of second dielectric layers with conductive layers.

公开(公告)号：US20230307361A1

公开(公告)日：2023-09-28

申请号：US17901644

申请日：2022-09-01

申请人： Kioxia Corporation

发明人： Yasunori IWASHITA ,  Shinya ARAI ,  Keisuke NAKATSUKA ,  Hiroaki ASHIDATE

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L27/11578 ,  H01L27/11551

CPC分类号： H01L23/5283 ,  H01L23/5226 ,  H01L27/11578 ,  H01L27/11551

摘要： A method of manufacturing a semiconductor device includes forming a first metal pad in each of a plurality of first regions on a first substrate so that warpage is generated on the first substrate. The method further includes forming a second metal pad in each of a plurality of second regions on a second substrate via a predetermined pattern. The method further includes bonding, after forming the first metal pad and the second metal pad, the first substrate with the second substrate. Moreover, the method further includes: making a correction, at a time of forming the predetermined pattern in each of the plurality of second regions on the second substrate, to change a position of the predetermined pattern in each of the plurality of second regions in a direction of being closer to a center of the second substrate for a first direction and to change the position of the predetermined pattern in a direction of being farther from the center of the second substrate for a second direction.

公开(公告)号：US20230301085A1

公开(公告)日：2023-09-21

申请号：US17699227

申请日：2022-03-21

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： Shih-Hung CHEN

IPC分类号： H01L27/11524 ,  G11C16/04 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/108

CPC分类号： H01L27/11524 ,  G11C16/0483 ,  H01L23/5283 ,  H01L23/5226 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/10805

摘要： A memory device includes a memory interposer, memory array regions, logic chips, and interconnection lines. The memory array regions are in the memory interposer, in which the memory array regions include at least one memory having NAND architecture. The logic chips are over the memory interposer. The interconnection lines connect the logic chips to each other, and connect the logic chips to the memory array regions.

公开(公告)号：US20230200063A1

公开(公告)日：2023-06-22

申请号：US17559725

申请日：2021-12-22

申请人： Intel Corporation

发明人： Deepak Thimmegowda ,  Chang Wan Ha ,  Md Rezaul Karim Nishat ,  Liu Liu ,  Yuanrong Shui ,  Kwame Eason ,  Ahmed Reza ,  Hoon Koh

IPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L23/48 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/04 ,  G11C8/14

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L23/481 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/0483 ,  G11C8/14

摘要： Systems, apparatuses, and methods may provide for technology that arranges stair wells for memory devices. The memory device includes a memory array and a memory block coupled to the memory array. The memory block includes a first through array via area and a first staircase area coupled to a plurality of decks. The first staircase area includes a first stair well and a second stair well located contiguous to the first stair well.

公开(公告)号：US11665898B2

公开(公告)日：2023-05-30

申请号：US17204487

申请日：2021-03-17

申请人： Kioxia Corporation

发明人： Daisuke Kawamura ,  Go Oike

IPC分类号： H01L27/11578 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11551

CPC分类号： H01L27/11578 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11573

摘要： A semiconductor device of an embodiment includes first and second structures arranged in a first hierarchy, in which the first and second structures are repeatedly arranged in a first direction along a plane of the first hierarchy, and a distance between geometric centers of the first and second structures in a minimum unit of repetition of the first and second structures differs between a first position and a second position in the first direction.

公开(公告)号：US20230157019A1

公开(公告)日：2023-05-18

申请号：US17527972

申请日：2021-11-16

申请人： SUNRISE MEMORY CORPORATION

发明人： Vinod Purayath ,  Wu-Yi Henry Chien

IPC分类号： H01L27/11578 ,  H01L27/11551

CPC分类号： H01L27/11578 ,  H01L27/11551

摘要： In the highly efficient fabrication processes for HNOR arrays provided herein, the channel regions of the storage transistors in the HNOR arrays are protected by a protective layer after deposition until the subsequent deposition of a charge-trapping material before forming local word lines. Both the silicon for the channel regions and the protective material may be deposited in amorphous form and are subsequently crystallized in an anneal step. The protective material may be silicon boron, silicon carbon or silicon germanium. The protective material induces greater grain boundaries in the crystallized silicon in the channel regions, thereby providing greater charge carrier mobility, greater conductivity and greater current densities.

公开(公告)号：US20190221582A1

公开(公告)日：2019-07-18

申请号：US16366857

申请日：2019-03-27

申请人： SK hynix Inc.

发明人： Ki Hong LEE ,  Seung Ho PYI ,  In Su PARK

IPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519 ,  H01L29/792 ,  H01L23/522 ,  H01L27/11551

CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block, second conductive layers stacked on the first conductive layer, and a second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block.

公开(公告)号：US20190157279A1

公开(公告)日：2019-05-23

申请号：US16237913

申请日：2019-01-02

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Youngbeom PYON ,  Kichul PARK ,  Inkwon KIM ,  Ki Hoon JANG ,  Byoungho KWON ,  Sangkyun KIM ,  Boun YOON

IPC分类号： H01L27/112 ,  H01L23/535 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11551 ,  H01L27/11578

CPC分类号： H01L27/11286 ,  H01L21/02107 ,  H01L21/76801 ,  H01L21/76819 ,  H01L23/528 ,  H01L23/535 ,  H01L23/538 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

摘要： A semiconductor device includes a substrate, a peripheral structure, a lower insulating layer, and a stack. The substrate includes a peripheral circuit region and a cell array region. The peripheral structure is on the peripheral circuit region. The lower insulating layer covers the peripheral circuit region and the cell array region and has a protruding portion protruding from a flat portion. The stack is on the lower insulating layer and the cell array region, and includes upper conductive patterns and insulating patterns which are alternately and repeatedly stacked.

公开(公告)号：US20180337197A1

公开(公告)日：2018-11-22

申请号：US16048412

申请日：2018-07-30

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei YAMAZAKI ,  Kensuke YOSHIZUMI

IPC分类号： H01L27/12 ,  H01L27/1156 ,  H01L27/04 ,  H01L27/06 ,  H01L27/108 ,  H01L29/423 ,  H01L21/84 ,  G11C16/10 ,  H01L27/11551 ,  H01L29/24 ,  H01L27/11521

CPC分类号： H01L27/1207 ,  G11C16/10 ,  H01L21/84 ,  H01L27/04 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203 ,  H01L29/24 ,  H01L29/42384

摘要： A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.