公开(公告)号：US20180121587A1

公开(公告)日：2018-05-03

申请号：US15645227

申请日：2017-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Udit MONGA ,  Jong Wook Jeon ,  Ken Machida ,  Ui Hui Kwon

IPC: G06F17/50 ,  G06F17/18

Abstract: A soft error rate (SER) associated with a design of a semiconductor circuit may be predicted based on implementing a simulation associated with the design. The simulation may include generating a simulation environment based on information indicating the design, performing a particle strike simulation based on the simulation environment to generate charge deposition information, and calculating a collected charge quantity from the charge deposition information. A determination may be made whether the SER predicted based on the collected charge quantity at least meets a threshold. The design may be modified, and the simulation repeated, if the predicted SER value meets a threshold value. A semiconductor circuit may be manufactured based on the design if the predicted SER value is less than the threshold value.