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Patent Agency Ranking
公开(公告)号：US20210165940A1
公开(公告)日：2021-06-03
申请号：US16919157
申请日：2020-07-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaehee Choi , Udit Monga , Ken Machida , Uihui Kwon , Yonghee Park
IPC: G06F30/3308
Abstract: A method of estimating aging of an integrated circuit (IC) includes: obtaining a first process design kit (PDK) including a plurality of first device models corresponding to a plurality of devices provided by a process of fabricating the IC; obtaining values of aging parameters of device instances included in a netlist defining the IC, by performing a first circuit simulation based on the netlist and the first PDK; and obtaining aging data of the IC by performing a second circuit simulation based on the values of the aging parameters and the netlist, wherein each of the plurality of first device models includes at least one measurement command to be executed in the first circuit simulation to calculate an aging parameter.
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公开(公告)号：US11972185B2
公开(公告)日：2024-04-30
申请号：US16919157
申请日：2020-07-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaehee Choi , Udit Monga , Ken Machida , Uihui Kwon , Yonghee Park
IPC: G06F30/3308 , G06F119/04
CPC classification number: G06F30/3308 , G06F2119/04
Abstract: A method of estimating aging of an integrated circuit (IC) includes: obtaining a first process design kit (PDK) including a plurality of first device models corresponding to a plurality of devices provided by a process of fabricating the IC; obtaining values of aging parameters of device instances included in a netlist defining the IC, by performing a first circuit simulation based on the netlist and the first PDK; and obtaining aging data of the IC by performing a second circuit simulation based on the values of the aging parameters and the netlist, wherein each of the plurality of first device models includes at least one measurement command to be executed in the first circuit simulation to calculate an aging parameter.
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公开(公告)号：US10566042B2
公开(公告)日：2020-02-18
申请号：US16169653
申请日：2018-10-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ken Machida , Yoshiaki Sonobe , Takeshi Kato
Abstract: Magnetic tunnel junction devices are provided. A magnetic tunnel junction device includes a pinned layer. The magnetic tunnel junction device includes a free layer on the pinned layer. The free layer includes a first layer, a second layer that is on the first layer, and a third layer that is between the first layer and the second layer. A Curie temperature of the third layer is lower than a Curie temperature of the first layer and lower than a Curie temperature of the second layer. Moreover, the magnetic tunnel junction device includes an insulating layer that is between the pinned layer and the free layer. Related magnetoresistive memory devices are also provided.
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公开(公告)号：US10783306B2
公开(公告)日：2020-09-22
申请号：US15645227
申请日：2017-07-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Udit Monga , Jong Wook Jeon , Ken Machida , Ui Hui Kwon
IPC: G06F30/367 , H01L29/78 , H01L27/088 , G06F17/18 , G06F111/20 , H01L23/556 , H01L23/60 , H01L29/06
Abstract: A soft error rate (SER) associated with a design of a semiconductor circuit may be predicted based on implementing a simulation associated with the design. The simulation may include generating a simulation environment based on information indicating the design, performing a particle strike simulation based on the simulation environment to generate charge deposition information, and calculating a collected charge quantity from the charge deposition information. A determination may be made whether the SER predicted based on the collected charge quantity at least meets a threshold. The design may be modified, and the simulation repeated, if the predicted SER value meets a threshold value. A semiconductor circuit may be manufactured based on the design if the predicted SER value is less than the threshold value.
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公开(公告)号：US20180121587A1
公开(公告)日：2018-05-03
申请号：US15645227
申请日：2017-07-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Udit MONGA , Jong Wook Jeon , Ken Machida , Ui Hui Kwon
Abstract: A soft error rate (SER) associated with a design of a semiconductor circuit may be predicted based on implementing a simulation associated with the design. The simulation may include generating a simulation environment based on information indicating the design, performing a particle strike simulation based on the simulation environment to generate charge deposition information, and calculating a collected charge quantity from the charge deposition information. A determination may be made whether the SER predicted based on the collected charge quantity at least meets a threshold. The design may be modified, and the simulation repeated, if the predicted SER value meets a threshold value. A semiconductor circuit may be manufactured based on the design if the predicted SER value is less than the threshold value.
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