公开(公告)号：US10950604B2

公开(公告)日：2021-03-16

申请号：US16908829

申请日：2020-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hyun Song ,  Yoon Suk Kim ,  Kyu Baik Chang ,  Ui Hui Kwon ,  Yo Han Kim ,  Jong Choi Kim ,  Chang Wook Jeong

IPC: H01L27/088 ,  H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

公开(公告)号：US20210151433A1

公开(公告)日：2021-05-20

申请号：US17161950

申请日：2021-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hyun Song ,  Yoon Suk Kim ,  Kyu Baik Chang ,  Ui Hui Kwon ,  Yo Han Kim ,  Jong Chol Kim ,  Chang Wook Jeong

IPC: H01L27/088 ,  H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L27/092

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

公开(公告)号：US20170162568A1

公开(公告)日：2017-06-08

申请号：US15370463

申请日：2016-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hyun Song ,  Yoon Suk Kim ,  Kyu Baik Chang ,  Ui Hui Kwon ,  Yo Han Kim ,  Jong Chol Kim ,  Chang Wook Jeong

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/785 ,  H01L29/7854

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

公开(公告)号：US20230170351A1

公开(公告)日：2023-06-01

申请号：US18097664

申请日：2023-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hyun Song ,  Yoon Suk Kim ,  Kyu Baik Chang ,  Ui Hui Kwon ,  Yo Han Kim ,  Jong Chol Kim ,  Chang Wook Jeong

IPC: H01L27/088 ,  H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L29/785 ,  H01L27/0207 ,  H01L29/0649 ,  H01L27/0924 ,  H01L21/823821

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

公开(公告)号：US09966446B2

公开(公告)日：2018-05-08

申请号：US15353163

申请日：2016-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Hee Park ,  Young Seok Song ,  Young Chul Hwang ,  Ui Hui Kwon ,  Keun Ho Lee ,  Jee Soo Chang ,  Jae Hee Choi

IPC: H01L29/76 ,  H01L29/417 ,  H01L29/78 ,  H01L23/532 ,  H01L23/522 ,  H01L29/66

CPC classification number: H01L29/41791 ,  H01L23/5226 ,  H01L23/5329 ,  H01L29/41775 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/7851

Abstract: There is provided a semiconductor device to enhance operating characteristics by reducing parasitic capacitance between a gate electrode and other nodes. The semiconductor device includes: a substrate including an active region, and a field region directly adjacent to the active region; a first fin-type pattern protruding from the substrate in the active region; a first gate electrode disposed on the substrate, intersecting with the first fin-type pattern and including a first portion and a second portion, the first portion intersecting with the first fin-type pattern; a second gate electrode disposed on the substrate, intersecting with the first fin-type pattern and including a third portion and a fourth portion, the fourth portion facing the second portion, and the third portion intersecting with the first fin-type pattern and facing the first portion; a first interlayer insulating structure disposed between the first portion and the third portion, being on the substrate, and having a first dielectric constant; and a second interlayer insulating structure disposed between the second portion and the fourth portion, being on the substrate, and having a second dielectric constant which is different from the first dielectric constant.

公开(公告)号：US12068367B2

公开(公告)日：2024-08-20

申请号：US17581026

申请日：2022-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Hyeok Kim ,  Jae-Hyun Yoo ,  Ui Hui Kwon ,  Kyu Ok Lee ,  Yong Woo Jeon ,  Da Won Jeong

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/42376 ,  H01L29/7816

Abstract: A semiconductor device includes a substrate, a gate electrode disposed on an upper surface of the substrate, a source region disposed on a first side of the gate electrode, a drain region disposed on a second side of the gate electrode opposite to the first side of the gate electrode in a horizontal direction, and an insulating structure at least partially buried inside the substrate on the substrate. The insulating structure includes a first portion disposed between the substrate and the gate electrode, and a second portion in contact with the drain region. An uppermost surface of the second portion of the insulating structure is lower than an uppermost surface of the first portion of the insulating structure. At least a part of the gate electrode is disposed on the uppermost surface of the second portion of the insulating structure.

公开(公告)号：US11581311B2

公开(公告)日：2023-02-14

申请号：US17161950

申请日：2021-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hyun Song ,  Yoon Suk Kim ,  Kyu Baik Chang ,  Ui Hui Kwon ,  Yo Han Kim ,  Jong Chol Kim ,  Chang Wook Jeong

IPC: H01L27/088 ,  H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

公开(公告)号：US20220406891A1

公开(公告)日：2022-12-22

申请号：US17581026

申请日：2022-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Hyeok Kim ,  Jae-Hyun Yoo ,  Ui Hui Kwon ,  Kyu Ok Lee ,  Yong Woo Jeon ,  Da Won Jeong

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, a gate electrode disposed on an upper surface of the substrate, a source region disposed on a first side of the gate electrode, a drain region disposed on a second side of the gate electrode opposite to the first side of the gate electrode in a horizontal direction, and an insulating structure at least partially buried inside the substrate on the substrate. The insulating structure includes a first portion disposed between the substrate and the gate electrode, and a second portion in contact with the drain region. An uppermost surface of the second portion of the insulating structure is lower than an uppermost surface of the first portion of the insulating structure. At least a part of the gate electrode is disposed on the uppermost surface of the second portion of the insulating structure.

公开(公告)号：US20200321334A1

公开(公告)日：2020-10-08

申请号：US16908829

申请日：2020-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hyun Song ,  Yoon Suk Kim ,  Kyu Baik Chang ,  Ui Hui Kwon ,  Yo Han Kim ,  Jong Chol Kim ,  Chang Wook Jeong

IPC: H01L27/088 ,  H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L27/092

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

公开(公告)号：US10783306B2

公开(公告)日：2020-09-22

申请号：US15645227

申请日：2017-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Udit Monga ,  Jong Wook Jeon ,  Ken Machida ,  Ui Hui Kwon

IPC: G06F30/367 ,  H01L29/78 ,  H01L27/088 ,  G06F17/18 ,  G06F111/20 ,  H01L23/556 ,  H01L23/60 ,  H01L29/06

Abstract: A soft error rate (SER) associated with a design of a semiconductor circuit may be predicted based on implementing a simulation associated with the design. The simulation may include generating a simulation environment based on information indicating the design, performing a particle strike simulation based on the simulation environment to generate charge deposition information, and calculating a collected charge quantity from the charge deposition information. A determination may be made whether the SER predicted based on the collected charge quantity at least meets a threshold. The design may be modified, and the simulation repeated, if the predicted SER value meets a threshold value. A semiconductor circuit may be manufactured based on the design if the predicted SER value is less than the threshold value.