公开(公告)号：US20230018676A1

公开(公告)日：2023-01-19

申请号：US17692693

申请日：2022-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YeongBeom KO

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: Provided is a semiconductor package, including a lower semiconductor chip, a plurality of semiconductor chips that are disposed on the lower semiconductor chip in a first direction perpendicular to a top surface of the lower semiconductor chip, a plurality of nonconductive layers disposed between the plurality of semiconductor chips, a nonconductive pattern that extends from the nonconductive layers and is disposed on lateral surfaces of at least one of the plurality of semiconductor chips, a first mold layer disposed a top surface of the nonconductive pattern, and a second mold layer disposed a lateral surface of the nonconductive pattern and a lateral surface of the first mold layer, wherein the nonconductive pattern and the first mold layer are disposed between the second mold layer and lateral surfaces of the plurality of semiconductor chips.

公开(公告)号：US20230260845A1

公开(公告)日：2023-08-17

申请号：US17896578

申请日：2022-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyun KWEON ,  YeongBeom KO ,  Wooju KIM ,  Heejae NAM ,  Jungseok RYU ,  Junho YOON

IPC: H01L21/8234 ,  H01L23/00

CPC classification number: H01L21/823437 ,  H01L21/823475 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/16145

Abstract: Disclosed are wafer structures and semiconductor devices. A semiconductor device may include a substrate and a cell array structure on the substrate. The substrate may include a device region and a dummy region surrounding the device region in a plan view. The cell array structure may include a plurality of first dielectric layers, a plurality of gate structures, a vertical channel structure, and a dummy pattern. The vertical channel structure may be on the device region and may penetrate the plurality of gate structures and the plurality of first dielectric layers. The cell array structure includes an outer sidewall above an edge of the substrate and a recessed portion on the outer sidewall of the cell array structure. The dummy pattern may cover a sidewall of the recessed portion and a bottom surface of the recessed portion. The dummy pattern and vertical channel structure may include a same material.