公开(公告)号：US20220415842A1

公开(公告)日：2022-12-29

申请号：US17537994

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongbeom KO ,  Wooju KIM ,  Heejae NAM ,  Jungseok RYU ,  Haemin PARK

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a semiconductor chip on a substrate. The semiconductor chip includes an active region, and a scribe lane in continuity with an edge of the active region. A non-conductive film (NCF) is between the substrate and the semiconductor chip, the non-conductive film (NCF) at least partially defines a recess region overlapping with the scribe lane in plan view and extending on the active region.

公开(公告)号：US20240297141A1

公开(公告)日：2024-09-05

申请号：US18659400

申请日：2024-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongbeom KO ,  Wooju KIM ,  Heejae NAM ,  Jungseok RYU ,  Haemin PARK

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/32 ,  H01L25/0657 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/32057 ,  H01L2224/32058 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2924/10156

Abstract: A semiconductor package includes a semiconductor chip on a substrate. The semiconductor chip includes an active region, and a scribe lane in continuity with an edge of the active region. A non-conductive film (NCF) is between the substrate and the semiconductor chip, the non-conductive film (NCF) at least partially defines a recess region overlapping with the scribe lane in plan view and extending on the active region.

公开(公告)号：US20230260845A1

公开(公告)日：2023-08-17

申请号：US17896578

申请日：2022-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyun KWEON ,  YeongBeom KO ,  Wooju KIM ,  Heejae NAM ,  Jungseok RYU ,  Junho YOON

IPC: H01L21/8234 ,  H01L23/00

CPC classification number: H01L21/823437 ,  H01L21/823475 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/16145

Abstract: Disclosed are wafer structures and semiconductor devices. A semiconductor device may include a substrate and a cell array structure on the substrate. The substrate may include a device region and a dummy region surrounding the device region in a plan view. The cell array structure may include a plurality of first dielectric layers, a plurality of gate structures, a vertical channel structure, and a dummy pattern. The vertical channel structure may be on the device region and may penetrate the plurality of gate structures and the plurality of first dielectric layers. The cell array structure includes an outer sidewall above an edge of the substrate and a recessed portion on the outer sidewall of the cell array structure. The dummy pattern may cover a sidewall of the recessed portion and a bottom surface of the recessed portion. The dummy pattern and vertical channel structure may include a same material.