公开(公告)号：US20230420352A1

公开(公告)日：2023-12-28

申请号：US18154261

申请日：2023-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongbeom KO ,  Junyun KWEON ,  Wooju KIM ,  Heejae NAM ,  Haemin PARK ,  Junggeun SHIN

IPC: H01L23/498 ,  H10B80/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49833 ,  H10B80/00 ,  H01L24/96 ,  H01L24/97 ,  H01L24/32 ,  H01L24/16 ,  H01L24/73 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3135 ,  H01L2924/182 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2224/95001 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L24/48 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73253

Abstract: A semiconductor package, comprising: a first redistribution structure including a first redistribution via; a first package that is on an upper surface of the first redistribution structure and comprises a first pad; a second redistribution structure that is on a lower surface of the first redistribution structure and comprises a second redistribution via; a second semiconductor chip that is between the first redistribution structure and the second redistribution structure and comprises a connection pad; and a vertical connection structure that is between the first redistribution structure and the second redistribution structure, wherein the vertical connection structure is electrically connected to the first redistribution via and the second redistribution via, the connection pad is electrically connected to the second redistribution via, and the first redistribution via is electrically connected to the first pad.

公开(公告)号：US20240297141A1

公开(公告)日：2024-09-05

申请号：US18659400

申请日：2024-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongbeom KO ,  Wooju KIM ,  Heejae NAM ,  Jungseok RYU ,  Haemin PARK

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/32 ,  H01L25/0657 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/32057 ,  H01L2224/32058 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2924/10156

Abstract: A semiconductor package includes a semiconductor chip on a substrate. The semiconductor chip includes an active region, and a scribe lane in continuity with an edge of the active region. A non-conductive film (NCF) is between the substrate and the semiconductor chip, the non-conductive film (NCF) at least partially defines a recess region overlapping with the scribe lane in plan view and extending on the active region.

公开(公告)号：US20230260845A1

公开(公告)日：2023-08-17

申请号：US17896578

申请日：2022-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyun KWEON ,  YeongBeom KO ,  Wooju KIM ,  Heejae NAM ,  Jungseok RYU ,  Junho YOON

IPC: H01L21/8234 ,  H01L23/00

CPC classification number: H01L21/823437 ,  H01L21/823475 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/16145

Abstract: Disclosed are wafer structures and semiconductor devices. A semiconductor device may include a substrate and a cell array structure on the substrate. The substrate may include a device region and a dummy region surrounding the device region in a plan view. The cell array structure may include a plurality of first dielectric layers, a plurality of gate structures, a vertical channel structure, and a dummy pattern. The vertical channel structure may be on the device region and may penetrate the plurality of gate structures and the plurality of first dielectric layers. The cell array structure includes an outer sidewall above an edge of the substrate and a recessed portion on the outer sidewall of the cell array structure. The dummy pattern may cover a sidewall of the recessed portion and a bottom surface of the recessed portion. The dummy pattern and vertical channel structure may include a same material.

公开(公告)号：US20240387460A1

公开(公告)日：2024-11-21

申请号：US18320553

申请日：2023-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heejae NAM ,  Junyun Kweon ,  Wooju Kim ,  Junggeun Shin

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package including a package substrate having an upper surface and a lower surface opposite to the upper surface, the package substrate having first substrate pads along a side portion thereof and second substrate pads outside the first substrate pads, being along the side portion, and arranged at positions higher than the first substrate pads, a first group of semiconductor chips sequentially stacked on the upper surface of the package substrate, and including at least one semiconductor chip, a second group of semiconductor chips sequentially stacked on the first group of semiconductor chips and including at least one semiconductor chip, first bonding wires electrically connecting chip pads of the first group of semiconductor chips to the first substrate pads, respectively, and second bonding wires electrically connecting chips pads of the second group of semiconductor chips to the second substrate pads, respectively may be provided.

公开(公告)号：US20220415842A1

公开(公告)日：2022-12-29

申请号：US17537994

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongbeom KO ,  Wooju KIM ,  Heejae NAM ,  Jungseok RYU ,  Haemin PARK

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a semiconductor chip on a substrate. The semiconductor chip includes an active region, and a scribe lane in continuity with an edge of the active region. A non-conductive film (NCF) is between the substrate and the semiconductor chip, the non-conductive film (NCF) at least partially defines a recess region overlapping with the scribe lane in plan view and extending on the active region.