公开(公告)号：US20230085734A1

公开(公告)日：2023-03-23

申请号：US17728275

申请日：2022-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunjae KIM ,  Chungho SONG ,  Yonghoe CHO

IPC: H01L27/146 ,  H01L23/00

Abstract: An image sensor package includes: a package base substrate having a cavity extending inwards from an upper surface thereof, and including a plurality of upper surface connection pads and a plurality of lower surface connection pads; an image sensor chip in the cavity, and including a chip body having a first surface and a second surface facing each other, a sensor unit located in the first surface of the chip body, and a plurality of chip pads around the sensor unit; a filter glass above the image sensor chip, and including a transparent substrate and a plurality of redistribution patterns on a lower surface of the transparent substrate; and a plurality of connection terminals between the plurality of redistribution patterns and the plurality of chip pads and between the plurality of redistribution patterns and the plurality of upper surface connection pads.

公开(公告)号：US20240170455A1

公开(公告)日：2024-05-23

申请号：US18226529

申请日：2023-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghoe CHO ,  Seunghoon YEON ,  SeungRyong OH

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/08148 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438

Abstract: A semiconductor package is provided that includes: a first semiconductor die, and a second semiconductor die on the first semiconductor die. The first semiconductor die includes a semiconductor substrate, a wiring layer on an active surface of the semiconductor substrate, a redistribution pattern on an inactive surface of the semiconductor substrate, a first passivation layer on the inactive surface of the semiconductor substrate wherein the first passivation layer is on the redistribution pattern and has an opening that exposes a top surface of the redistribution pattern, and a backside pad on the first passivation layer and coupled through the opening to the redistribution pattern. An inner lateral surface of the opening is inclined at an angle of 90 to 105 degrees relative to the top surface of the redistribution pattern. A thickness of the first passivation layer is 0.3 to 0.5 times a thickness of the redistribution pattern.

公开(公告)号：US20210028102A1

公开(公告)日：2021-01-28

申请号：US16809116

申请日：2020-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghoon Yeon ,  Wonil LEE ,  Yonghoe CHO

IPC: H01L23/522 ,  H01L23/498 ,  H01L23/48 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor device having a through silicon via, a lower redistribution structure on the semiconductor device, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the through silicon via, a package connection terminal on the lower redistribution structure and electrically connected to the lower redistribution pattern, an upper redistribution structure on the semiconductor device and including an upper redistribution insulating layer and an upper redistribution pattern electrically connected to the through silicon via, a conductive via in contact with the upper redistribution pattern and on the upper redistribution insulating layer, a connection pad on the conductive via, and a passive element pattern on the upper redistribution structure and electrically connected to the conductive via.

公开(公告)号：US20220262689A1

公开(公告)日：2022-08-18

申请号：US17733411

申请日：2022-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoeun KIM ,  Yonghoe CHO ,  Sunkyoung SEO ,  Seunghoon YEON ,  Sanguk HAN

IPC: H01L21/66 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00 ,  G01R31/28 ,  G01R27/26

Abstract: A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.

公开(公告)号：US20190214359A1

公开(公告)日：2019-07-11

申请号：US16044696

申请日：2018-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghoon YEON ,  Hyoeun KIM ,  Jongbo SHIM ,  Yonghoe CHO

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor package may include a base layer, and a redistribution layer on the base layer. The semiconductor package may include a first pattern, a second pattern, and a passivation layer covering the first and second patterns. The semiconductor package may include a semiconductor chip on the base layer, a first connection terminal between the base layer and the semiconductor chip and coupled to one of chip pads of the semiconductor chip, and a mold layer between the base layer and the semiconductor chip. The first connection terminal may extend into the passivation layer and may be coupled to the first pattern. The second pattern may be electrically insulated from the semiconductor chip.