公开(公告)号：US20230138813A1

公开(公告)日：2023-05-04

申请号：US17978507

申请日：2022-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunkyoung SEO ,  Chajea JO ,  Yeongseon KIM ,  Juhyeon KIM ,  Hyoeun KIM

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: A first semiconductor chip includes a first semiconductor substrate, a first wiring structure arranged on the first semiconductor substrate, a plurality of through electrodes penetrating through at least a portion of the first semiconductor substrate, and a plurality of first bonding pads respectively connected to the plurality of through electrodes. A second semiconductor chip is stacked on the first semiconductor chip and includes a second semiconductor substrate, a second wiring structure arranged on the second semiconductor substrate, and a second bonding pad connected to each of the plurality of first bonding pads and arranged on the active surface of the second semiconductor substrate. Each first bonding pad has a top surface that is in direct contact with the second bonding pad and a bottom surface that is in direct contact with one through electrode.

公开(公告)号：US20220262689A1

公开(公告)日：2022-08-18

申请号：US17733411

申请日：2022-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoeun KIM ,  Yonghoe CHO ,  Sunkyoung SEO ,  Seunghoon YEON ,  Sanguk HAN

IPC: H01L21/66 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00 ,  G01R31/28 ,  G01R27/26

Abstract: A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.

公开(公告)号：US20190214359A1

公开(公告)日：2019-07-11

申请号：US16044696

申请日：2018-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghoon YEON ,  Hyoeun KIM ,  Jongbo SHIM ,  Yonghoe CHO

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor package may include a base layer, and a redistribution layer on the base layer. The semiconductor package may include a first pattern, a second pattern, and a passivation layer covering the first and second patterns. The semiconductor package may include a semiconductor chip on the base layer, a first connection terminal between the base layer and the semiconductor chip and coupled to one of chip pads of the semiconductor chip, and a mold layer between the base layer and the semiconductor chip. The first connection terminal may extend into the passivation layer and may be coupled to the first pattern. The second pattern may be electrically insulated from the semiconductor chip.

公开(公告)号：US20240290669A1

公开(公告)日：2024-08-29

申请号：US18385082

申请日：2023-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunkyoung SEO ,  Dohyun KIM ,  Yeongseon KIM ,  Juhyeon KIM ,  Hyoeun KIM ,  Jeongoh HA

IPC: H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L22/32 ,  H01L24/08 ,  H01L25/0657 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/1436

Abstract: A semiconductor structure according to an embodiment may include: an interconnect structure on a substrate; an interlayer dielectric layer on the interconnect structure; a first conductive pad within the interlayer dielectric layer and electrically coupled with the interconnect structure; a second conductive pad within the interlayer dielectric layer and electrically decoupled from the interconnect structure; a first via plug within the interlayer dielectric layer; and a bonding structure on the interlayer dielectric layer and including a first bonding pad, a plurality of second bonding pads, and a bonding dielectric layer, wherein the first bonding pad is electrically coupled to the first via plug, some of the plurality of second bonding pads are spaced apart from the first conductive pad in a vertical direction, and others of the plurality of second bonding pads are spaced apart from the second conductive pad in the vertical direction.

公开(公告)号：US20230117072A1

公开(公告)日：2023-04-20

申请号：US18066487

申请日：2022-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chajea JO ,  Ohguk KWON ,  Namhoon KIM ,  Hyoeun KIM ,  Seunghoon YEON

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

Abstract: An integrated circuit device includes a semiconductor substrate, first through-silicon-via (TSV) structures penetrating a first region of the semiconductor substrate and spaced apart from each other by a first pitch, a first individual device between the first TSV structures and spaced apart from the first TSV structures by a distance that is greater than a first keep-off distance, and second TSV structures penetrating a second region of the semiconductor substrate and spaced apart from each other by a second pitch that is less than the first pitch. The second region of the semiconductor device does not include an individual device that is homogeneous with the first individual device and between the second TSV structures.

公开(公告)号：US20210407890A1

公开(公告)日：2021-12-30

申请号：US17162418

申请日：2021-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chajea JO ,  Ohguk KWON ,  Namhoon KIM ,  Hyoeun KIM ,  Seunghoon YEON

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768

Abstract: An integrated circuit device includes a semiconductor substrate, first through-silicon-via (TSV) structures penetrating a first region of the semiconductor substrate and spaced apart from each other by a first pitch, a first individual device between the first TSV structures and spaced apart from the first TSV structures by a distance that is greater than a first keep-off distance, and second TSV structures penetrating a second region of the semiconductor substrate and spaced apart from each other by a second pitch that is less than the first pitch. The second region of the semiconductor device does not include an individual device that is homogeneous with the first individual device and between the second TSV structures.

公开(公告)号：US20210193581A1

公开(公告)日：2021-06-24

申请号：US17003639

申请日：2020-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunkyoung SEO ,  Taehwan KIM ,  Hyunjung SONG ,  Hyoeun KIM ,  Wonil LEE ,  Sanguk HAN

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/367

Abstract: A semiconductor package includes a package substrate, a lower semiconductor device arranged on the package substrate and including first through electrodes, first lower connection bumps arranged between the package substrate and the lower semiconductor device and electrically connecting the package substrate to the first through electrodes, a connecting substrate arranged on the package substrate and including second through electrodes, second lower connection bumps arranged between the package substrate and the connecting substrate and electrically connecting the package substrate to the second through electrodes, and an upper semiconductor device arranged on the lower semiconductor device and electrically connected to the first through electrodes and the second through electrodes.

公开(公告)号：US20240243153A1

公开(公告)日：2024-07-18

申请号：US18405372

申请日：2024-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjun CHOI ,  Jihyun KWAK ,  Hyoeun KIM ,  Surim LEE

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L27/14634 ,  H01L23/5223 ,  H01L24/08 ,  H01L24/80 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: An image sensor is provided. The image sensor includes a first semiconductor chip including a first semiconductor substrate having a pixel unit, a first wiring structure having a first wiring layer, and a first bonding pad; a second semiconductor chip including a second semiconductor substrate having first and second surfaces, a second wiring structure on the first surface, contacting the first wiring structure, and having a second wiring layer, a second upper bonding pad bonded to the first bonding pad, and a via structure connected to the second wiring layer and extending to the second surface; a bonding layer including a bonding insulating layer on the second surface, and a second lower bonding pad connected to the via structure; and a third semiconductor chip including a third semiconductor substrate, a third wiring structure contacting the bonding insulating layer, and a third bonding pad bonded to the second lower bonding pad.

公开(公告)号：US20220157780A1

公开(公告)日：2022-05-19

申请号：US17375511

申请日：2021-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ohguk KWON ,  Namhoon KIM ,  Hyoeun KIM ,  Sunkyoung SEO

IPC: H01L25/065 ,  H01L23/538

Abstract: A semiconductor package including a substrate; a first semiconductor chip on the substrate; a second semiconductor chip on the first semiconductor chip; and at least one connection terminal between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip includes a first semiconductor chip body; and at least one upper pad on a top surface of the first semiconductor chip body and in contact with the at least one connection terminal, the at least one upper pad includes a recess that is downwardly recessed from a top surface thereof, and a depth of the recess is less than a thickness of the at least one upper pad.