公开(公告)号：US11961551B2

公开(公告)日：2024-04-16

申请号：US17585865

申请日：2022-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo Bong Chang ,  Young-Il Lim ,  Bok-Yeon Won ,  Seok Jae Lee ,  Dong Geon Kim ,  Myeong Sik Ryu ,  In Seok Baek ,  Kyoung Min Kim ,  Sang Wook Park

IPC: G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4091 ,  G11C11/4094

Abstract: A bitline sense amplifier including: an amplifier which is connected between a first sensing bitline and a second sensing bitline, and detects and amplifies a voltage difference between a first bitline and a second bitline in response to a first control signal and a second control signal; and an equalizer which is connected between a first supply line through which the first control signal is supplied and a second supply line through which the second control signal is supplied, and pre-charges the first bitline and the second bitline with a precharge voltage in response to an equalizing control signal, wherein the equalizer includes an equalizing enable transistor in which a source terminal is connected to the first supply line and performs equalizing in response to the equalizing control signal.

公开(公告)号：US20130215662A1

公开(公告)日：2013-08-22

申请号：US13748773

申请日：2013-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Il Lim ,  Cheol Kim ,  Sang-Ho Shin

IPC: G11C17/00

CPC classification number: G11C17/00 ,  G11C17/16 ,  G11C29/785

Abstract: A memory device includes an anti-fuse cell array including a plurality of anti-fuse cells. Each anti-fuse cell includes a first cell transistor connected to a common node, a second cell transistor connected to the common node, and an access transistor connected to the common node. The first cell transistor is configured to store data and the second cell transistor is configured to store data when the first cell transistor has defect data.

Abstract translation: 存储器件包括包括多个反熔丝单元的反熔丝单元阵列。 每个反熔丝单元包括连接到公共节点的第一单元晶体管，连接到公共节点的第二单元晶体管和连接到公共节点的存取晶体管。 第一单元晶体管被配置为存储数据，并且第二单元晶体管被配置为当第一单元晶体管具有缺陷数据时存储数据。

公开(公告)号：US08976564B2

公开(公告)日：2015-03-10

申请号：US13748773

申请日：2013-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Il Lim ,  Cheol Kim ,  Sang-Ho Shin

IPC: G11C17/00 ,  G11C17/16 ,  G11C29/00

CPC classification number: G11C17/00 ,  G11C17/16 ,  G11C29/785

Abstract: A memory device includes an anti-fuse cell array including a plurality of anti-fuse cells. Each anti-fuse cell includes a first cell transistor connected to a common node, a second cell transistor connected to the common node, and an access transistor connected to the common node. The first cell transistor is configured to store data and the second cell transistor is configured to store data when the first cell transistor has defect data.

Abstract translation: 存储器件包括包括多个反熔丝单元的反熔丝单元阵列。 每个反熔丝单元包括连接到公共节点的第一单元晶体管，连接到公共节点的第二单元晶体管和连接到公共节点的存取晶体管。 第一单元晶体管被配置为存储数据，并且第二单元晶体管被配置为当第一单元晶体管具有缺陷数据时存储数据。