公开(公告)号：US09208837B2

公开(公告)日：2015-12-08

申请号：US13975134

申请日：2013-08-23

Applicant: Samsung Electronics Co., Ltd

Inventor： Sei-Jin Kim ,  Sang-Ho Shin ,  Hee-Sub Shin

IPC: G06F13/00 ,  G11C7/10 ,  G11C7/22 ,  G06F3/06 ,  G06F3/00

CPC classification number: G11C7/1072 ,  G06F3/0611 ,  G06F3/0646 ,  G06F3/0689 ,  G11C7/22 ,  G11C2207/2236

Abstract: The present disclosure relates to an apparatus and method capable of carrying out data movement in a memory of a terminal. The apparatus includes a processor configured to transmit a command for data movement and address information for data movement in a memory to the memory, and the memory configured to perform the data movement in units of word line in the memory by using the address information, in response to reception of the command for moving the data.

Abstract translation: 本公开涉及能够在终端的存储器中执行数据移动的装置和方法。 该装置包括：处理器，被配置为向存储器发送用于数据移动的命令和用于数据移动的地址信息，以及被配置为通过使用地址信息以存储器中的字线为单位执行数据移动的处理器， 响应接收到用于移动数据的命令。

公开(公告)号：US08988962B2

公开(公告)日：2015-03-24

申请号：US13749687

申请日：2013-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Ho Shin ,  Jung-Bae Lee ,  Min-Jeung Cho

IPC: G11C7/00 ,  G11C11/402 ,  G11C11/406

CPC classification number: G11C11/402 ,  G11C11/40618

Abstract: A refresh circuit and a semiconductor memory device including the refresh circuit are disclosed. The refresh circuit includes a mode register, a refresh controller and a multiplexer circuit. The mode register generates a mode register signal having information relating to a memory bank on which a refresh operation is to be performed. The refresh controller generates a self-refresh active command and a self-refresh address based on a self-refresh command and an oscillation signal. The multiplexer circuit may include a plurality of multiplexers. Each of the multiplexers selects one of an active command and the self-refresh active command in response to bits of the mode register signal. Each of the multiplexers generates a row active signal based on the selected command, and selects one of an external address and the self-refresh address to generate a row address.

Abstract translation: 公开了一种刷新电路和包括刷新电路的半导体存储器件。 刷新电路包括模式寄存器，刷新控制器和多路复用器电路。 模式寄存器生成具有与要进行刷新操作的存储体有关的信息的模式寄存器信号。 刷新控制器基于自刷新命令和振荡信号产生自刷新活动命令和自刷新地址。 多路复用器电路可以包括多个多路复用器。 每个复用器响应于模式寄存器信号的位选择一个活动命令和自刷新活动命令。 每个多路复用器基于所选择的命令生成行活动信号，并且选择外部地址和自刷新地址之一以生成行地址。

公开(公告)号：US20140059285A1

公开(公告)日：2014-02-27

申请号：US13975134

申请日：2013-08-23

Applicant: Samsung Electronics Co., Ltd

Inventor： Sei-Jin Kim ,  Sang-Ho Shin ,  Hee-Sub Shin

IPC: G11C7/10 ,  G06F3/06

CPC classification number: G11C7/1072 ,  G06F3/0611 ,  G06F3/0646 ,  G06F3/0689 ,  G11C7/22 ,  G11C2207/2236

Abstract: The present disclosure relates to an apparatus and method capable of carrying out data movement in a memory of a terminal. The apparatus includes a processor configured to transmit a command for data movement and address information for data movement in a memory to the memory, and the memory configured to perform the data movement in units of word line in the memory by using the address information, in response to reception of the command for moving the data.

Abstract translation: 本公开涉及能够在终端的存储器中执行数据移动的装置和方法。 该装置包括：处理器，被配置为向存储器发送用于数据移动的命令和用于数据移动的地址信息，以及被配置为通过使用地址信息以存储器中的字线为单位执行数据移动的处理器， 响应接收到用于移动数据的命令。

公开(公告)号：US20130215662A1

公开(公告)日：2013-08-22

申请号：US13748773

申请日：2013-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Il Lim ,  Cheol Kim ,  Sang-Ho Shin

IPC: G11C17/00

CPC classification number: G11C17/00 ,  G11C17/16 ,  G11C29/785

Abstract: A memory device includes an anti-fuse cell array including a plurality of anti-fuse cells. Each anti-fuse cell includes a first cell transistor connected to a common node, a second cell transistor connected to the common node, and an access transistor connected to the common node. The first cell transistor is configured to store data and the second cell transistor is configured to store data when the first cell transistor has defect data.

Abstract translation: 存储器件包括包括多个反熔丝单元的反熔丝单元阵列。 每个反熔丝单元包括连接到公共节点的第一单元晶体管，连接到公共节点的第二单元晶体管和连接到公共节点的存取晶体管。 第一单元晶体管被配置为存储数据，并且第二单元晶体管被配置为当第一单元晶体管具有缺陷数据时存储数据。

公开(公告)号：US09570132B2

公开(公告)日：2017-02-14

申请号：US14803119

申请日：2015-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol Kim ,  Young-soo Sohn ,  Sang-Ho Shin

IPC: G11C8/00 ,  G11C8/06 ,  H01L25/065 ,  G11C29/00

CPC classification number: G11C8/06 ,  G11C29/76 ,  G11C29/785 ,  H01L25/0657 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory chip includes a chip input-output pad unit, a plurality of semiconductor dies. The chip input-output pad unit includes a plurality of input-output pins connected to an external device and the plurality of semiconductor dies are connected commonly to the chip input-output pad unit and having a full memory capacity respectively. Each semiconductor die includes a die input-output pad unit, a memory region and a conversion block. The die input-output pad unit includes a plurality of input-output terminals respectively connected to the input-output pins of the chip input-output pad unit. The memory region includes an activated region corresponding to a portion of the full memory capacity and a deactivated region corresponding to a remainder portion of the full memory capacity. The conversion block connects the activated region except the deactivated region to the die input-output pad unit.

Abstract translation: 存储器芯片包括芯片输入 - 输出焊盘单元，多个半导体管芯。 芯片输入输出焊盘单元包括连接到外部设备的多个输入输出引脚，并且多个半导体管芯分别连接到芯片输入 - 输出焊盘单元并具有完全存储器容量。 每个半导体管芯包括管芯输入 - 输出焊盘单元，存储区域和转换块。 管芯输入 - 输出焊盘单元包括分别连接到芯片输入 - 输出焊盘单元的输入 - 输出引脚的多个输入 - 输出端子。 存储器区域包括对应于全部存储器容量的一部分的激活区域和对应于完整存储器容量的剩余部分的去激活区域。 转换块将去激活区域之外的激活区域连接到管芯输入 - 输出焊盘单元。

公开(公告)号：US08976564B2

公开(公告)日：2015-03-10

申请号：US13748773

申请日：2013-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Il Lim ,  Cheol Kim ,  Sang-Ho Shin

IPC: G11C17/00 ,  G11C17/16 ,  G11C29/00

CPC classification number: G11C17/00 ,  G11C17/16 ,  G11C29/785

Abstract: A memory device includes an anti-fuse cell array including a plurality of anti-fuse cells. Each anti-fuse cell includes a first cell transistor connected to a common node, a second cell transistor connected to the common node, and an access transistor connected to the common node. The first cell transistor is configured to store data and the second cell transistor is configured to store data when the first cell transistor has defect data.

Abstract translation: 存储器件包括包括多个反熔丝单元的反熔丝单元阵列。 每个反熔丝单元包括连接到公共节点的第一单元晶体管，连接到公共节点的第二单元晶体管和连接到公共节点的存取晶体管。 第一单元晶体管被配置为存储数据，并且第二单元晶体管被配置为当第一单元晶体管具有缺陷数据时存储数据。

公开(公告)号：US20130124735A1

公开(公告)日：2013-05-16

申请号：US13674566

申请日：2012-11-12

Applicant: Samsung Electronics Co., Ltd

Inventor： Sang-Ho Shin ,  Su-Bong Kim ,  Hyo-Sun Shim ,  Joong-Hwan Lee ,  Myong-Kyun Lim ,  Jin-Hyeon Choi

IPC: G06F15/173

CPC classification number: H04L61/2007 ,  H04L29/06 ,  H04L61/256 ,  H04L61/2582 ,  H04L61/2589

Abstract: An operating method of a device for provisioning a Network Address Translator (NAT) traversal technique includes connecting to a network, determining whether a plurality of NAT traversal techniques is operable using a server over the connected network, and storing information of an operable NAT traversal technique among the plurality of the NAT traversal techniques. Thus, the connection setup time between the devices can be shortened.

Abstract translation: 用于提供网络地址转换器（NAT）遍历技术的设备的操作方法包括连接到网络，确定多个NAT遍历技术是否可以通过所连接的网络使用服务器来操作，以及存储可操作的NAT穿越技术的信息 在多个NAT穿越技术中。 因此，可以缩短设备之间的连接建立时间。