公开(公告)号：US20200373243A1

公开(公告)日：2020-11-26

申请号：US16671625

申请日：2019-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegwon JANG ,  lnwon O ,  Jongyoun KIM ,  Seokhyun LEE ,  Yeonho JANG

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a mold substrate, at least one semiconductor chip disposed in the mold substrate and including chip pads, and a redistribution wiring layer covering a first surface of the mold substrate and including a first redistribution wiring and a second redistribution wiring stacked in at least two levels to be electrically connected to the chip pads. The first redistribution wiring includes a signal line extending in a first region, and the second redistribution wiring includes a ground line in a second region overlapping with the first region. The ground line has a plurality of through holes of polygonal column shapes.