公开(公告)号：US20240170408A1

公开(公告)日：2024-05-23

申请号：US18426995

申请日：2024-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inhyung SONG ,  Kyoung Lim SUK ,  Jaegwon JANG ,  Wonkyoung CHOI

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5384 ,  H01L23/3114 ,  H01L23/5386 ,  H01L24/14

Abstract: A semiconductor package includes a first semiconductor device on a first redistribution substrate, a first mold layer that covers the first semiconductor device and the first redistribution substrate, and a second redistribution substrate on the first mold layer, the second redistribution substrate including a first opening that exposes a top surface of the first mold layer, a sidewall of the second redistribution substrate that is exposed to the first opening having a stepwise structure.

公开(公告)号：US20210111114A1

公开(公告)日：2021-04-15

申请号：US16884212

申请日：2020-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun LEE ,  Jongyoun KIM ,  Yeonho JANG ,  Jaegwon JANG

IPC: H01L23/498 ,  H01L21/48

Abstract: A semiconductor package includes a semiconductor chip, a redistribution structure below the semiconductor chip, a first insulating layer below the redistribution structure, a pad below the first insulating layer, the pad being in contact with the redistribution structure, and a bump below the pad, wherein a horizontal maximum length of an upper portion of the pad is greater than a horizontal maximum length of a lower portion of the pad.

公开(公告)号：US20170141050A1

公开(公告)日：2017-05-18

申请号：US15293786

申请日：2016-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegwon JANG ,  Youngjae KIM ,  Baikwoo LEE

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3121 ,  H01L24/13 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15151 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A printed circuit board includes chip regions on which semiconductor chips are mounted, and a scribe region surrounding each of the chip regions. The scribe region includes first vent holes that are configured to receive a flow of molding resin and are arranged along a first direction corresponding to a flow direction of the molding resin.

公开(公告)号：US20250105178A1

公开(公告)日：2025-03-27

申请号：US18634322

申请日：2024-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： MinKi AHN ,  Kwangho LEE ,  Heeseok LEE ,  Jaegwon JANG ,  Heejung CHOI

IPC: H01L23/00

Abstract: A semiconductor chip according to an embodiment includes a semiconductor substrate, an interconnection pad on a first surface of the semiconductor substrate, an insulation layer being on the first surface of the semiconductor substrate and defining an opening that exposes at least a partial portion of the interconnection pad, a capping pad being on the insulation layer and being connected to the interconnection pad through the opening, and an insulation structure at a periphery of the capping pad on the insulation layer.

公开(公告)号：US20240096815A1

公开(公告)日：2024-03-21

申请号：US18244739

申请日：2023-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaegwon JANG ,  Inhyung SONG ,  Yeonho JANG

IPC: H01L23/544 ,  H01L23/498 ,  H01L25/10 ,  H01L25/16

CPC classification number: H01L23/544 ,  H01L23/49822 ,  H01L25/105 ,  H01L25/16 ,  H01L24/48 ,  H01L2223/54426 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A semiconductor package includes: a first package substrate including a first redistribution structure; a second package substrate including a second redistribution structure; a semiconductor chip provided between the first package substrate and the second package substrate, and attached to the first package substrate; and a fiducial mark provided on the second package substrate and separated from the second redistribution structure in a plan view.

公开(公告)号：US20220406702A1

公开(公告)日：2022-12-22

申请号：US17892215

申请日：2022-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun LEE ,  Jongyoun KIM ,  Yeonho JANG ,  Jaegwon JANG

IPC: H01L23/498 ,  H01L21/48

Abstract: A semiconductor package includes a semiconductor chip, a redistribution structure below the semiconductor chip, a first insulating layer below the redistribution structure, a pad below the first insulating layer, the pad being in contact with the redistribution structure, and a bump below the pad, wherein a horizontal maximum length of an upper portion of the pad is greater than a horizontal maximum length of a lower portion of the pad.

公开(公告)号：US20200373243A1

公开(公告)日：2020-11-26

申请号：US16671625

申请日：2019-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegwon JANG ,  lnwon O ,  Jongyoun KIM ,  Seokhyun LEE ,  Yeonho JANG

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a mold substrate, at least one semiconductor chip disposed in the mold substrate and including chip pads, and a redistribution wiring layer covering a first surface of the mold substrate and including a first redistribution wiring and a second redistribution wiring stacked in at least two levels to be electrically connected to the chip pads. The first redistribution wiring includes a signal line extending in a first region, and the second redistribution wiring includes a ground line in a second region overlapping with the first region. The ground line has a plurality of through holes of polygonal column shapes.

公开(公告)号：US20240021608A1

公开(公告)日：2024-01-18

申请号：US18478056

申请日：2023-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung Lim SUK ,  Seokhyun LEE ,  Jaegwon JANG

IPC: H01L27/08 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L27/0805 ,  H01L23/5222 ,  H01L23/5386 ,  H01L24/14 ,  H01L28/60

Abstract: Disclosed is a semiconductor package including: a redistribution substrate; at least one passive device in the redistribution substrate, the passive device including a first terminal and a second terminal; and a semiconductor chip on a top surface of the redistribution substrate, the semiconductor chip vertically overlapping at least a portion of the passive device, wherein the redistribution substrate includes: a dielectric layer in contact with a first lateral surface, a second lateral surface opposite to the first lateral surface, and a bottom surface of the passive device; a lower conductive pattern on the first terminal; a lower seed pattern provided between the first terminal and the conductive pattern, and directly connected to the first terminal; a first upper conductive pattern on the second terminal and a first upper seed pattern provided between the second terminal and the first upper conductive pattern, and directly connected to the second terminal

公开(公告)号：US20230071812A1

公开(公告)日：2023-03-09

申请号：US17846245

申请日：2022-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaegwon JANG ,  Kyounglim SUK ,  Inhyung SONG

IPC: H01L25/065 ,  H01L25/10 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a substrate including a redistribution layer, a chip structure including a first semiconductor chip disposed on the substrate and including a first through-electrode, a second semiconductor chip disposed on the first semiconductor chip and electrically connected to the first semiconductor chip by the first through-electrode, and a first encapsulant at least partially surrounding the second semiconductor chip. A first connection bump disposed between the substrate and the chip structure and electrically connects the first through-electrode to the redistribution layer, a second connection bump disposed below the substrate and electrically connects to the redistribution layer, and a second encapsulant e the chip structure on the substrate. The first semiconductor chip is connected to and faces the second semiconductor chip.

公开(公告)号：US20220157810A1

公开(公告)日：2022-05-19

申请号：US17359110

申请日：2021-06-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung Lim SUK ,  Seokhyun LEE ,  Jaegwon JANG

IPC: H01L27/08 ,  H01L23/00 ,  H01L23/538 ,  H01L23/522 ,  H01L49/02

Abstract: Disclosed is a semiconductor package including: a redistribution substrate; at least one passive device in the redistribution substrate, the passive device including a first terminal and a second terminal; and a semiconductor chip on a top surface of the redistribution substrate, the semiconductor chip vertically overlapping at least a portion of the passive device, wherein the redistribution substrate includes: a dielectric layer in contact with a first lateral surface, a second lateral surface opposite to the first lateral surface, and a bottom surface of the passive device; a lower conductive pattern on the first terminal; a lower seed pattern provided between the first terminal and the conductive pattern, and directly connected to the first terminal; a first upper conductive pattern on the second terminal and a first upper seed pattern provided between the second terminal and the first upper conductive pattern, and directly connected to the second terminal