公开(公告)号：US11694755B2

公开(公告)日：2023-07-04

申请号：US17337329

申请日：2021-06-02

Applicant: SanDisk Technologies LLC

Inventor： Hiroyuki Mizukoshi ,  Heguang Li ,  Althaf Rahamathulla ,  Qihan Li

IPC: G11C16/34 ,  G11C29/02 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/3481 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3459 ,  G11C29/021

Abstract: An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. The control circuits are configured to abort fine programming of the plurality of non-volatile memory cells at an intermediate stage and read the plurality of non-volatile memory cells at the intermediate stage to obtain first partial data of at least one logical page. The control circuits are configured obtain the at least one logical page of data by combining the first partial data with second partial data of the at least one logical page stored in data latches.

公开(公告)号：US20220392555A1

公开(公告)日：2022-12-08

申请号：US17337329

申请日：2021-06-02

Applicant: SanDisk Technologies LLC

Inventor： Hiroyuki Mizukoshi ,  Heguang Li ,  Althaf Rahamathulla ,  Qihan Li

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C29/02

Abstract: An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. The control circuits are configured to abort fine programming of the plurality of non-volatile memory cells at an intermediate stage and read the plurality of non-volatile memory cells at the intermediate stage to obtain first partial data of at least one logical page. The control circuits are configured obtain the at least one logical page of data by combining the first partial data with second partial data of the at least one logical page stored in data latches.