摘要:
A decoding apparatus and method in a BWA communication system are provided, in which an ID-based decoder controller detects an ID from a data block by partially decoding the data block, and if the ID indicates that the data block is not for the receiver, outputs a control signal commanding non-decoding for the data block, a bitmap table controller indicates the data block as a non-decoding data block in a bitmap table according to the control signal, and a decoder distinguishes data blocks to be decoded from non-decoding data blocks based on the bitmap table, decodes the data blocks to be decoded and outputs the decoded data blocks, and simply outputs the non-decoding data blocks without decoding.
摘要:
A decoding apparatus and method in a BWA communication system are provided, in which an ID-based decoder controller detects an ID from a data block by partially decoding the data block, and if the ID indicates that the data block is not for the receiver, outputs a control signal commanding non-decoding for the data block, a bitmap table controller indicates the data block as a non-decoding data block in a bitmap table according to the control signal, and a decoder distinguishes data blocks to be decoded from non-decoding data blocks based on the bitmap table, decodes the data blocks to be decoded and outputs the decoded data blocks, and simply outputs the non-decoding data blocks without decoding.
摘要:
An apparatus and method for processing input/output data in a communication system is disclosed. By adding a controller that adjusts timing intervals between a first buffer having a first timing interval and a second buffer having a second timing interval, buffer usage can be minimized.
摘要:
A high speed input buffer device for a turbo decoder and an input method thereof are provided. The input buffer device comprises a combing buffer for outputting stored symbols based on read addresses; a write MUX for dividing the output symbols into systematic, parity-1, and parity-2 symbols based on a BitSel signal, and outputting the divided symbols, first and second de-first rate matchers for individually performing a de-first rate matching operation with respect to the parity-1 and parity-2 symbols output from the write MUX, a data conversion unit generating code words, each of which contains a systematic symbol, a parity-1 symbol, and a parity-2 symbol, by using the systematic symbols output from the write MUX and the de-first-rate-matched parity-1 and parity-2 symbols, an input buffer unit having a double buffer structure, containing code blocks corresponding to the plurality of turbo decoders, storing each of the code words in a memory area of a code block corresponding to a decoder distinction signal which represents one of the turbo decodes, and outputting the stored code words to relevant turbo decoders, and a buffer controller for providing the input buffer unit with the decoder distinction signal, and providing the write MUX with the BitSel signal for dividing the output symbols into systematic, parity-1, and parity-2 symbols. Since the number and the area of memory elements required for the input control for a decoder are reduced, processing time, the error occurrence rate upon realizing the chip, and power consumption can be reduced.