公开(公告)号：US08379510B2

公开(公告)日：2013-02-19

申请号：US11984367

申请日：2007-11-16

申请人： Sang-Hyo Kim ,  Weon-Heum Park ,  Jong-Han Lim

发明人： Sang-Hyo Kim ,  Weon-Heum Park ,  Jong-Han Lim

IPC分类号： G01R31/08

CPC分类号： H04L5/023 ,  H04L1/0045 ,  H04L1/0053 ,  H04L27/2647

摘要： A decoding apparatus and method in a BWA communication system are provided, in which an ID-based decoder controller detects an ID from a data block by partially decoding the data block, and if the ID indicates that the data block is not for the receiver, outputs a control signal commanding non-decoding for the data block, a bitmap table controller indicates the data block as a non-decoding data block in a bitmap table according to the control signal, and a decoder distinguishes data blocks to be decoded from non-decoding data blocks based on the bitmap table, decodes the data blocks to be decoded and outputs the decoded data blocks, and simply outputs the non-decoding data blocks without decoding.

摘要翻译： 提供了一种在BWA通信系统中的解码装置和方法，其中基于ID的解码器控制器通过部分地解码数据块来从数据块检测ID，并且如果ID指示数据块不是用于接收器， 输出命令对数据块进行非解码的控制信号，位图表控制器根据控制信号将数据块指示为位图表中的非解码数据块，并且解码器将要解码的数据块与非解码数据块进行区分， 基于位图表解码数据块，对要解码的数据块进行解码，并输出解码的数据块，并且在不进行解码的情况下简单地输出非解码数据块。

公开(公告)号：US20080117996A1

公开(公告)日：2008-05-22

申请号：US11984367

申请日：2007-11-16

申请人： Sang-Hyo Kim ,  Weon-Heum Park ,  Jong-Han Lim

发明人： Sang-Hyo Kim ,  Weon-Heum Park ,  Jong-Han Lim

IPC分类号： H04L23/02 ,  H04L5/12

CPC分类号： H04L5/023 ,  H04L1/0045 ,  H04L1/0053 ,  H04L27/2647

摘要： A decoding apparatus and method in a BWA communication system are provided, in which an ID-based decoder controller detects an ID from a data block by partially decoding the data block, and if the ID indicates that the data block is not for the receiver, outputs a control signal commanding non-decoding for the data block, a bitmap table controller indicates the data block as a non-decoding data block in a bitmap table according to the control signal, and a decoder distinguishes data blocks to be decoded from non-decoding data blocks based on the bitmap table, decodes the data blocks to be decoded and outputs the decoded data blocks, and simply outputs the non-decoding data blocks without decoding.

摘要翻译： 提供了一种在BWA通信系统中的解码装置和方法，其中基于ID的解码器控制器通过部分地解码数据块来从数据块检测ID，并且如果ID指示数据块不是用于接收器， 输出命令对数据块进行非解码的控制信号，位图表控制器根据控制信号将数据块指示为位图表中的非解码数据块，并且解码器将要解码的数据块与非解码数据块进行区分， 基于位图表解码数据块，对要解码的数据块进行解码，并输出解码的数据块，并且在不进行解码的情况下简单地输出非解码数据块。

公开(公告)号：US20070189233A1

公开(公告)日：2007-08-16

申请号：US11655053

申请日：2007-01-18

申请人： Dong-Wook Park ,  Hyun-Bae Lee ,  Weon-Heum Park ,  Gang-Mi Gil ,  Hyun-Seok Yu

发明人： Dong-Wook Park ,  Hyun-Bae Lee ,  Weon-Heum Park ,  Gang-Mi Gil ,  Hyun-Seok Yu

IPC分类号： H04B7/216

CPC分类号： H04L1/0052 ,  H04L1/0067 ,  H04L1/0071

摘要： An apparatus and method for processing input/output data in a communication system is disclosed. By adding a controller that adjusts timing intervals between a first buffer having a first timing interval and a second buffer having a second timing interval, buffer usage can be minimized.

摘要翻译： 公开了一种在通信系统中处理输入/输出数据的装置和方法。 通过添加调整具有第一定时间隔的第一缓冲器和具有第二定时间隔的第二缓冲器之间的定时间隔的控制器，可以最小化缓冲器使用。

公开(公告)号：US20060101319A1

公开(公告)日：2006-05-11

申请号：US11267214

申请日：2005-11-07

申请人： Dong-Wook Park ,  Joo-Kwang Kim ,  Weon-Heum Park

发明人： Dong-Wook Park ,  Joo-Kwang Kim ,  Weon-Heum Park

IPC分类号： H03M13/00

CPC分类号： H03M13/635 ,  H03M13/2957

摘要： A high speed input buffer device for a turbo decoder and an input method thereof are provided. The input buffer device comprises a combing buffer for outputting stored symbols based on read addresses; a write MUX for dividing the output symbols into systematic, parity-1, and parity-2 symbols based on a BitSel signal, and outputting the divided symbols, first and second de-first rate matchers for individually performing a de-first rate matching operation with respect to the parity-1 and parity-2 symbols output from the write MUX, a data conversion unit generating code words, each of which contains a systematic symbol, a parity-1 symbol, and a parity-2 symbol, by using the systematic symbols output from the write MUX and the de-first-rate-matched parity-1 and parity-2 symbols, an input buffer unit having a double buffer structure, containing code blocks corresponding to the plurality of turbo decoders, storing each of the code words in a memory area of a code block corresponding to a decoder distinction signal which represents one of the turbo decodes, and outputting the stored code words to relevant turbo decoders, and a buffer controller for providing the input buffer unit with the decoder distinction signal, and providing the write MUX with the BitSel signal for dividing the output symbols into systematic, parity-1, and parity-2 symbols. Since the number and the area of memory elements required for the input control for a decoder are reduced, processing time, the error occurrence rate upon realizing the chip, and power consumption can be reduced.

摘要翻译： 提供了一种用于turbo解码器的高速输入缓冲器及其输入方法。 输入缓冲器件包括一个梳状缓冲器，用于基于读取地址输出存储的符号; 写入MUX，用于根据BitSel信号将输出符号分成系统的，奇偶校验位1和奇偶校验2符号，并输出分割的符号，第一和第二去先速率匹配器，用于单独执行解除速率匹配操作 相对于从写入MUX输出的奇偶校验1和奇偶校验2符号，数据转换单元通过使用第一和第二奇偶校验符号生成代码字，每个代码字包含系统符号，奇偶校验1符号和奇偶校验符号2 从写入MUX和解除速率匹配的奇偶校验1和奇偶校验2符号输出的系统符号，具有双缓冲结构的输入缓冲器单元，其包含与多个turbo解码器相对应的代码块， 与代表turbo解码的解码器区分信号相对应的代码块的存储器区域中的代码字，并将存储的代码字输出到相关的turbo解码器;以及缓冲器控制器，用于向输入缓冲器单元提供 解码器区分信号，以及向写MUX提供BitSel信号，以将输出符号分成系统的，奇偶校验位1和奇偶校验符号2。 由于减少了解码器的输入控制所需的存储器元件的数量和面积，因此可以减少处理时间，实现芯片时的出错率和功耗。